Journals in DBLP
David W. Knapp , Alice C. Parker The ADAM design planning engine. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:7, pp:829-846 [Journal ] Elizabeth D. Lagnese , Donald E. Thomas Architectural partitioning for system level synthesis of integrated circuits. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:7, pp:847-860 [Journal ] Chandramouli Visweswariah , Ronald A. Rohrer Piecewise approximate circuit simulation. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:7, pp:861-870 [Journal ] Saul A. Kravitz , Randal E. Bryant , Rob A. Rutenbar Massively parallel switch-level simulation: a feasibility study. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:7, pp:871-894 [Journal ] K. K. Low , Stephen W. Director A new methodology for the design centering of IC fabrication processes. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:7, pp:895-903 [Journal ] Walter Guggenbühl , Guy Morbach , Michael Schaller Simulation lossless symmetrical three conductor systems. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:7, pp:904-910 [Journal ] Yen-Chuen Wei , Chung-Kuan Cheng Ratio cut partitioning for hierarchical designs. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:7, pp:911-921 [Journal ] Larry G. Jones Fast batch incremental netlist compilation hierarchical schematics. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:7, pp:922-931 [Journal ] Andres R. Takach , Niraj K. Jha Easily testable gate-level and DCVS multipliers. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:7, pp:932-942 [Journal ] Sreejit Chakravarty , Xin He , S. S. Ravi Minimum area layout of series-parallel transistor networks is NP-hard. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:7, pp:943-949 [Journal ] Jiri Vlach , James A. Barby , Anthony Vannelli , T. Talkhan , C.-J. Richard Shi Group delay as an estimate of delay in logic. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:7, pp:949-953 [Journal ]