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Journals in DBLP

IEEE Trans. on CAD of Integrated Circuits and Systems
2000, volume: 19, number: 8

  1. Tamal Mukherjee, L. Richard Carley, Rob A. Rutenbar
    Efficient handling of operating range and manufacturing linevariations in analog cell synthesis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:8, pp:825-839 [Journal]
  2. Shigeru Yamashita, Hiroshi Sawada, Akira Nagoya
    SPFD: A new method to express functional flexibility. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:8, pp:840-849 [Journal]
  3. Pak K. Chan, Martine D. F. Schlag, Carl Ebeling, Larry McMurchie
    Distributed-memory parallel routing for field-programmable gatearrays. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:8, pp:850-862 [Journal]
  4. Indradeep Ghosh, Sujit Dey, Niraj K. Jha
    A fast and low-cost testing technique for core-based system-chips. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:8, pp:863-877 [Journal]
  5. Grzegorz Mrugalski, Janusz Rajski, Jerzy Tyszer
    Cellular automata-based test pattern generators with phase shifters. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:8, pp:878-893 [Journal]
  6. Srivaths Ravi, Ganesh Lakshminarayana, Niraj K. Jha
    TAO-BIST: A framework for testability analysis and optimization forbuilt-in self-test of RTL circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:8, pp:894-906 [Journal]
  7. Paul Tafertshofer, Andreas Ganz, Kurt Antreich
    IGRAINE-an Implication GRaph-bAsed engINE for fast implication, justification, and propagation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:8, pp:907-927 [Journal]
  8. Huan-Chih Tsai, Kwang-Ting Cheng, Sudipta Bhawmik
    On improving test quality of scan-based BIST. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:8, pp:928-938 [Journal]
  9. Karsten Strehl, Lothar Thiele
    Interval diagrams for efficient symbolic verification of processnetworks. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:8, pp:939-956 [Journal]
  10. Ilker Hamzaoglu, Janak H. Patel
    Test set compaction algorithms for combinational circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:8, pp:957-963 [Journal]
  11. Ming-Bo Lin
    On the design of fast large fan-in CMOS multiplexers. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:8, pp:963-967 [Journal]
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