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Journals in DBLP

IEEE Trans. on CAD of Integrated Circuits and Systems
2002, volume: 21, number: 6

  1. Geert Van der Plas, Jan Vandenbussche, Georges G. E. Gielen, Willy M. C. Sansen
    A layout synthesis methodology for array-type analog blocks. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:6, pp:645-661 [Journal]
  2. Fei Yuan, Ajoy Opal
    An efficient transient analysis algorithm for mildly nonlinearcircuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:6, pp:662-673 [Journal]
  3. Gi-Joon Nam, Karem A. Sakallah, Rob A. Rutenbar
    A new FPGA detailed routing approach via search-based Booleansatisfiability. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:6, pp:674-684 [Journal]
  4. Min Ouyang, Michel Toulouse, Krishnaiyan Thulasiraman, Fred Glover, Jitender S. Deogun
    Multilevel cooperative search for the circuit/hypergraphpartitioning problem. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:6, pp:685-693 [Journal]
  5. Wanli Jiang, Bapiraju Vinnakota
    Statistical threshold formulation for dynamic Idd test. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:6, pp:694-705 [Journal]
  6. Irith Pomeranz, Sudhakar M. Reddy
    Test compaction for at-speed testing of scan circuits based onnonscan test. sequences and removal of transfer sequences. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:6, pp:706-714 [Journal]
  7. Anshuman Chandra, Krishnendu Chakrabarty
    Test data compression and decompression based on internal scanchains and Golomb coding. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:6, pp:715-722 [Journal]
  8. Yungseon Eo, Jongin Shim, William R. Eisenstadt
    A traveling-wave-based waveform approximation technique for thetiming verification of single transmission lines. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:6, pp:723-730 [Journal]
  9. Antoni Ferré, Joan Figueras
    Leakage power bounds in CMOS digital technologies. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:6, pp:731-738 [Journal]
  10. Y. Shin, T. Sakurai
    Power distribution analysis of VLSI interconnects using model orderreduction. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:6, pp:739-745 [Journal]
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