Journals in DBLP

IEEE Trans. on CAD of Integrated Circuits and Systems
1995, volume: 14, number: 1

1. Werner Geurts, Francky Catthoor, Hugo De Man
   Quadratic zero-one programming-based synthesis of application-specific data paths. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:1, pp:1-11 [Journal]
   
2. Anantha P. Chandrakasan, Miodrag Potkonjak, Renu Mehra, Jan M. Rabaey, Robert W. Brodersen
   Optimizing power using transformations. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:1, pp:12-31 [Journal]
   
3. William K. Lam, Alexander Saldanha, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
   Delay fault coverage, test set size, and performance trade-offs. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:1, pp:32-44 [Journal]
   
4. Luciano Lavagno, Cho W. Moon, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
   An efficient heuristic procedure for solving the state assignment problem for event-based specifications. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:1, pp:45-60 [Journal]
   
5. Luciano Lavagno, Kurt Keutzer, Alberto L. Sangiovanni-Vincentelli
   Synthesis of hazard-free asynchronous circuits with bounded wire delays. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:1, pp:61-86 [Journal]
   
6. Amelia Shen, Srinivas Devadas, Abhijit Ghosh
   Probabilistic manipulation of Boolean functions using free Boolean diagrams. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:1, pp:87-95 [Journal]
   
7. L. James Hwang, Abbas El Gamal
   Min-cut replication in partitioned networks. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:1, pp:96-106 [Journal]
   
8. Enrico Malavasi, Davide Pandini
   Optimum CMOS stack generation with analog constraints. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:1, pp:107-122 [Journal]
   
9. Peichen Pan, C. L. Liu
   Area minimization for floorplans. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:1, pp:123-132 [Journal]