Journals in DBLP

IEEE Trans. on CAD of Integrated Circuits and Systems
2004, volume: 23, number: 7

1. Takahiro J. Yamaguchi, Mani Soma, Jim Nissen, David Halter, Rajesh Raina, Masahiro Ishida
   Skew measurements in clock distribution circuits using an analytic signal method. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:7, pp:997-1009 [Journal]
   
2. Weidong Wang, Anand Raghunathan, Niraj K. Jha, Sujit Dey
   Resource budgeting for Multiprocess High-level synthesis. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:7, pp:1010-1019 [Journal]
   
3. Sunil P. Khatri, Subarnarekha Sinha, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
   SPFD-based wire removal in standard-cell and network-of-PLA circuits. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:7, pp:1020-1030 [Journal]
   
4. Peter Petrov, Alex Orailoglu
   Tag compression for low power in dynamically customizable embedded processors. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:7, pp:1031-1047 [Journal]
   
5. Xun Liu, Marios C. Papaefthymiou
   A Markov chain sequence generator for power macromodeling. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:7, pp:1048-1062 [Journal]
   
6. Eng Teo Ong, Heow Pueh Lee, Kian Meng Lim
   A parallel fast Fourier transform on multipoles (FFTM) algorithm for electrostatics analysis of three-dimensional structures. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:7, pp:1063-1072 [Journal]
   
7. Cliff C. N. Sze, Ting-Chi Wang, Li-C. Wang
   Multilevel circuit clustering for delay minimization. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:7, pp:1073-1085 [Journal]
   
8. Xiaohai Wu, Xianlong Hong, Yici Cai, Zuying Luo, Chung-Kuan Cheng, Jun Gu, Wayne Wei-Ming Dai
   Area minimization of power distribution network using efficient nonlinear programming techniques. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:7, pp:1086-1094 [Journal]
   
9. Sheng Uei Guan, Syn Kiat Tan
   Pseudorandom number generation with self-programmable cellular automata. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:7, pp:1095-1101 [Journal]
   
10. Ying-Tsai Chang, Kwang-Ting Cheng
    Self-referential verification for gate-level implementations of arithmetic circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:7, pp:1102-1112 [Journal]
    
11. Edmund M. Clarke, Anubhav Gupta, Ofer Strichman
    SAT-based counterexample-guided abstraction refinement. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:7, pp:1113-1123 [Journal]
    
12. Ching-An Lin, Chien-Hsien Wu
    Second-order approximations for RLC trees. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:7, pp:1124-1128 [Journal]
    
13. Mohsen Nahvi, André Ivanov
    Indirect test architecture for SoC testing. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:7, pp:1128-1142 [Journal]
    
14. Paul M. Rosinger, Bashir M. Al-Hashimi, Nicola Nicolici
    Scan architecture with mutually exclusive scan segment activation for shift- and capture-power reduction. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:7, pp:1142-1153 [Journal]