Journals in DBLP

IEEE Trans. on CAD of Integrated Circuits and Systems
2000, volume: 19, number: 1

1. C.-J. Richard Shi, Sheldon X.-D. Tan
   Canonical symbolic analysis of large analog circuits withdeterminant decision diagrams. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:1, pp:1-18 [Journal]
   
2. Chantana Chantrapornchai, Edwin Hsing-Mean Sha, Xiaobo Sharon Hu
   Efficient design exploration based on module utility selection. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:1, pp:19-29 [Journal]
   
3. Miodrag Potkonjak, Jan M. Rabaey
   Maximally and arbitrarily fast implementation of linear andfeedback linear computations. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:1, pp:30-43 [Journal]
   
4. Youpyo Hong, Peter A. Beerel, Jerry R. Burch, Kenneth L. McMillan
   Sibling-substitution-based BDD minimization using don't cares. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:1, pp:44-55 [Journal]
   
5. Steven J. E. Wilton
   Heterogeneous technology mapping for area reduction in FPGAs withembedded memory arrays. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:1, pp:56-68 [Journal]
   
6. Mahbub Hasan, Huan-Hsiang Patrick Shen, David R. Allee, Michael J. Pennell
   A behavioral model of a 1.8-V flash A/D converter based on deviceparameters. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:1, pp:69-82 [Journal]
   
7. Yehea I. Ismail, Eby G. Friedman, José Luis Neves
   Equivalent Elmore delay for RLC trees. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:1, pp:83-97 [Journal]
   
8. Tuyen V. Nguyen, Anirudh Devgan, Ognen J. Nastov, David W. Winston
   Transient sensitivity computation in controlled explicit piecewiselinear simulation. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:1, pp:98-110 [Journal]
   
9. Indradeep Ghosh, Niraj K. Jha, Sudipta Bhawmik
   A BIST scheme for RTL circuits based on symbolic testabilityanalysis. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:1, pp:111-128 [Journal]
   
10. Wanli Jiang, Bapiraju Vinnakota
    IC test using the energy consumption ratio. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:1, pp:129-141 [Journal]
    
11. Zheng Rong Yang, Mark Zwolinski, Chris D. Chalk, Alan Christopher Williams
    Applying a robust heteroscedastic probabilistic neural network toanalog fault detection and classification. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:1, pp:142-151 [Journal]
    
12. Shih-Chieh Chang, Wen-Ben Jone, Shi-Sen Chang
    TAIR: testability analysis by implication reasoning. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:1, pp:152-160 [Journal]
    
13. H. M. Chen, G. S. Samudra, D. S. H. Chan, Yaacob Ibrahim
    Global optimization for digital MOS circuits performance. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:1, pp:161-164 [Journal]
    
14. Spiridon Nikolaidis, E. Karaolis, Efstathios D. Kyriakis-Bitzaros
    Estimation of signal transition activity in FIR filters implementedby a MAC architecture. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:1, pp:164-169 [Journal]