Journals in DBLP

IEEE Trans. on CAD of Integrated Circuits and Systems
2001, volume: 20, number: 6

1. Amir H. Farrahi, Chunhong Chen, Ankur Srivastava, Gustavo E. Téllez, Majid Sarrafzadeh
   Activity-driven clock design. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:6, pp:705-714 [Journal]
   
2. Jaewon Oh, Massoud Pedram
   Gated clock routing for low-power microprocessor design. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:6, pp:715-722 [Journal]
   
3. Amr G. Wassal, M. Anwar Hasan
   Low-power system-level design of VLSI packet switching fabrics. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:6, pp:723-738 [Journal]
   
4. Jason Cong, David Zhigang Pan
   Interconnect performance estimation models for design planning. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:6, pp:739-752 [Journal]
   
5. Peter Meuris, Wim Schoenmaker, Wim Magnus
   Strategy for electromagnetic interconnect modeling. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:6, pp:753-762 [Journal]
   
6. Junlin Zhou, Mengzhang Cheng, Leonard Forbes
   SPICE models for flicker noise in p-MOSFETs in the saturationregion. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:6, pp:763-767 [Journal]
   
7. Kanishka Lahiri, Anand Raghunathan, Sujit Dey
   System-level performance analysis for designing on-chipcommunication architectures. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:6, pp:768-783 [Journal]
   
8. Yao-Wen Chang, Jai-Ming Lin, Martin D. F. Wong
   Matching-based algorithm for FPGA channel segmentation design. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:6, pp:784-791 [Journal]
   
9. Irith Pomeranz, Sudhakar M. Reddy
   On diagnosis and diagnostic test generation for pattern-dependenttransition faults. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:6, pp:791-800 [Journal]
   
10. Evangeline F. Y. Young, Martin D. F. Wong, Hannah Honghua Yang
    On extending slicing floorplan to handle L/T-shaped modules andabutment constraints. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:6, pp:800-807 [Journal]