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Journals in DBLP

IEEE Trans. on CAD of Integrated Circuits and Systems
1996, volume: 15, number: 10

  1. Khalid Rahmat, Jacob K. White, Dimitri A. Antoniadis
    Simulation of semiconductor devices using a Galerkin/spherical harmonic expansion approach to solving the coupled Poisson-Boltzmann system. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:10, pp:1181-1196 [Journal]
  2. Margarida F. Jacome, Stephen W. Director
    A formal basis for design process planning and management. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:10, pp:1197-1210 [Journal]
  3. Ashutosh Mujumdar, Rajiv Jain, Kewal K. Saluja
    Incorporating performance and testability constraints during binding in high-level synthesis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:10, pp:1212-1225 [Journal]
  4. Shih-Chieh Chang, Malgorzata Marek-Sadowska, TingTing Hwang
    Technology mapping for TLU FPGAs based on decomposition of binary decision diagrams. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:10, pp:1226-1236 [Journal]
  5. Sachin S. Sapatnekar, Rahul B. Deokar
    Utilizing the retiming-skew equivalence in a practical algorithm for retiming large circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:10, pp:1237-1248 [Journal]
  6. Kuo-Hua Wang, TingTing Hwang, Cheng Chen
    Exploiting communication complexity for Boolean matching. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:10, pp:1249-1256 [Journal]
  7. Tan-Li Chou, Kaushik Roy
    Estimation of activity for static and domino CMOS circuits considering signal correlations and simultaneous switching. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:10, pp:1257-1265 [Journal]
  8. S. E. Laux
    On particle-mesh coupling in Monte Carlo semiconductor device simulation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:10, pp:1266-1277 [Journal]
  9. Daniel G. Saab, Youssef Saab, Jacob A. Abraham
    Automatic test vector cultivation for sequential VLSI circuits using genetic algorithms. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:10, pp:1278-1285 [Journal]
  10. José T. de Sousa, Fernando M. Gonçalves, João Paulo Teixeira, Cristoforo Marzocca, Francesco Corsi, Thomas W. Williams
    Defect level evaluation in an IC design environment. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:10, pp:1286-1293 [Journal]
  11. Dorit S. Hochbaum
    An optimal test compression procedure for combinational circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:10, pp:1294-1299 [Journal]
  12. Kazuhiro Tsuchiya, Yoshiyasu Takefuji
    A neural network approach to PLA folding problems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:10, pp:1299-1305 [Journal]
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