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Journals in DBLP

IEEE Trans. on CAD of Integrated Circuits and Systems
2005, volume: 24, number: 9

  1. Zhiyuan Wang, Malgorzata Marek-Sadowska, Kun-Han Tsai, Janusz Rajski
    Delay-fault diagnosis using timing information. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:9, pp:1315-1325 [Journal]
  2. Valeriy Sukharev
    Physically based simulation of electromigration-induced degradation mechanisms in dual-inlaid copper interconnects. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:9, pp:1326-1335 [Journal]
  3. Medha Kulkarni, Tom Chen
    A sensitivity-based approach to analyzing signal delay uncertainty of coupled interconnects. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:9, pp:1336-1346 [Journal]
  4. Jianwen Zhu, Fang Fang, Qianying Tang
    Calligrapher: a new layout-migration engine for hard intellectual property libraries. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:9, pp:1347-1361 [Journal]
  5. Man Lung Mui, Kaustav Banerjee, Amit Mehrotra
    Supply and power optimization in leakage-dominant technologies. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:9, pp:1362-1371 [Journal]
  6. Manidip Sengupta, Sharad Saxena, Lidia Daldoss, Glen Kramer, Sean Minehane, Jianjun Cheng
    Application-specific worst case corners using response surfaces and statistical models. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:9, pp:1372-1380 [Journal]
  7. Carl-Johan H. Seger, Robert B. Jones, John W. O'Leary, Thomas F. Melham, Mark Aagaard, Clark Barrett, Don Syme
    An industrially effective environment for formal hardware verification. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:9, pp:1381-1405 [Journal]
  8. Yajun Ran, Alex Kondratyev, Kenneth H. Tseng, Yosinori Watanabe, Malgorzata Marek-Sadowska
    Eliminating false positives in crosstalk noise analysis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:9, pp:1406-1419 [Journal]
  9. Shu Yan, Vivek Sarin, Weiping Shi
    Sparse transformations and preconditioners for 3-D capacitance extraction. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:9, pp:1420-1426 [Journal]
  10. Hao Gang Wang, Chi Hou Chan, Leung Tsang
    A new multilevel Green's function interpolation method for large-scale low-frequency EM simulations. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:9, pp:1427-1443 [Journal]
  11. Young-Su Kwon, Chong-Min Kyung
    Performance-driven event-based synchronization for multi-FPGA simulation accelerator with event time-multiplexing bus. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:9, pp:1444-1456 [Journal]
  12. Dhiraj K. Pradhan, Chunsheng Liu
    EBIST: a novel test generator with built-in fault detection capability. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:9, pp:1457-1466 [Journal]
  13. Hongliang Chang, Sachin S. Sapatnekar
    Statistical timing analysis under spatial correlations. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:9, pp:1467-1482 [Journal]
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