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Journals in DBLP

IEEE Trans. on CAD of Integrated Circuits and Systems
1997, volume: 16, number: 3

  1. Yatin Vasant Hoskote, Jacob A. Abraham, Donald S. Fussell, John Moondanos
    Automatic verification of implementations of large circuits against HDL specifications. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:3, pp:217-228 [Journal]
  2. Liang-Fang Chao, Andrea S. LaPaugh, Edwin Hsing-Mean Sha
    Rotation scheduling: a loop pipelining algorithm. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:3, pp:229-239 [Journal]
  3. Rajesh K. Gupta, Giovanni De Micheli
    Specification and analysis of timing constraints for embedded systems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:3, pp:240-256 [Journal]
  4. Santanu Chattopadhyay, Samir Roy, Parimal Pal Chaudhuri
    KGPMIN: an efficient multilevel multioutput AND-OR-XOR minimizer. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:3, pp:257-265 [Journal]
  5. Wolfgang Kunz, Dominik Stoffel, Premachandran R. Menon
    Logic optimization and equivalence checking by implication analysis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:3, pp:266-281 [Journal]
  6. Wai-Kei Mak, Martin D. F. Wong
    On optimal board-level routing for FPGA-based logic emulation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:3, pp:282-289 [Journal]
  7. Ashok Vittal, Malgorzata Marek-Sadowska
    Crosstalk reduction for VLSI. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:3, pp:290-298 [Journal]
  8. Shung-Chih Chen, Jer-Min Jou
    Diagnostic fault simulation for synchronous sequential circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:3, pp:299-308 [Journal]
  9. Dimitrios Kagaris, Spyros Tragoudas, Dimitrios Karayiannis
    Improved nonenumerative path-delay fault-coverage estimation based on optimal polynomial-time algorithms. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:3, pp:309-315 [Journal]
  10. Shiuann-Shiuh Lin, Yuh-Ju Lin, TingTing Hwang
    Net assignment for the FPGA-based logic emulation system in the folded-Clos network structure. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:3, pp:316-320 [Journal]
  11. Alicja Pierzynska, Slawomir Pilarski
    Pitfalls in delay fault testing. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:3, pp:321-329 [Journal]
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