Journals in DBLP

IEEE Trans. on CAD of Integrated Circuits and Systems
1999, volume: 18, number: 7

1. Aiguo Xie, Peter A. Beerel
   Accelerating Markovian analysis of asynchronous systems using state compression. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:7, pp:869-888 [Journal]
   
2. Arun N. Lokanathan, Jay B. Brockman
   A methodology for concurrent process-circuit optimization. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:7, pp:889-902 [Journal]
   
3. Henrik Hulgaard, Poul Frederick Williams, Henrik Reif Andersen
   Equivalence checking of combinational circuits using Boolean expression diagrams. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:7, pp:903-917 [Journal]
   
4. Manish Pandey, Randal E. Bryant
   Exploiting symmetry when verifying transistor-level circuits by symbolic trajectory evaluation. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:7, pp:918-935 [Journal]
   
5. Sheetanshu L. Pandey, Kothanda Umamageswaran, Philip A. Wilsey
   VHDL semantics and validating transformations. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:7, pp:936-955 [Journal]
   
6. Sofiène Tahar, Xiaoyu Song, Eduard Cerny, Zijian Zhou, Michel Langevin, Otmane Aït Mohamed
   Modeling and formal verification of the Fairisle ATM switch fabricusing MDGs. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:7, pp:956-972 [Journal]
   
7. Radu Marculescu, Diana Marculescu, Massoud Pedram
   Sequence compaction for power estimation: theory and practice. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:7, pp:973-993 [Journal]
   
8. Youxin Gao, Martin D. F. Wong
   Optimal shape function for a bidirectional wire under Elmore delay model. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:7, pp:994-999 [Journal]
   
9. Christoph Maier, Markus Emmenegger, Stefano Taschini, Henry Baltes, Jan G. Korvink
   Equivalent circuit model of resistive IC sensors derived with the box integration method. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:7, pp:1000-1013 [Journal]
   
10. Chung-Ping Chen, Chris C. N. Chu, Martin D. F. Wong
    Fast and exact simultaneous gate and wire sizing by Lagrangian relaxation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:7, pp:1014-1025 [Journal]
    
11. Giri Devarayanadurg, Mani Soma, Prashant Goteti, Sam D. Huynh
    Test set selection for structural faults in analog IC's. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:7, pp:1026-1039 [Journal]
    
12. Irith Pomeranz, Sudhakar M. Reddy, Ruifeng Guo
    Static test compaction for synchronous sequential circuits based on vector restoration. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:7, pp:1040-1049 [Journal]
    
13. Spyros Tragoudas, Dimitrios Karayiannis
    A fast nonenumerative automatic test pattern generator for pathdelay faults. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:7, pp:1050-1057 [Journal]