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Journals in DBLP

IEEE Trans. on CAD of Integrated Circuits and Systems
1995, volume: 14, number: 2

  1. Mariusz Niewczas, Adam Wojtasik
    Modeling of VLSI RC parasitics based on the network reduction algorithm. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:2, pp:137-144 [Journal]
  2. Ching-Wei Yeh, Chung-Kuan Cheng, Ting-Ting Y. Lin
    Optimization by iterative improvement: an experimental evaluation on two-way partitioning. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:2, pp:145-153 [Journal]
  3. Ching-Wei Yeh, Chung-Kuan Cheng, Ting-Ting Y. Lin
    Circuit clustering using a stochastic flow injection method. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:2, pp:154-162 [Journal]
  4. Benjamín Iñíguez, Eugenio García Moreno
    Development of a Cinfinity-continuous small-signal model for a MOS transistor in normal operation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:2, pp:163-166 [Journal]
  5. Zhixin Yan, M. Jamal Deen
    New RTD large-signal DC model suitable for PSPICE. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:2, pp:167-172 [Journal]
  6. Chun-Jung Chen, Wu-Shiung Feng
    Relaxation-based transient sensitivity computations for MOSFET circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:2, pp:173-185 [Journal]
  7. Eli Chiprout, Michel S. Nakhla
    Analysis of interconnect networks using complex frequency hopping (CFH). [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:2, pp:186-200 [Journal]
  8. Chen-Liang Fang, Wen-Ben Jone
    Timing optimization by gate resizing and critical path identification. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:2, pp:201-217 [Journal]
  9. Christofer Toumazou, Costas A. Makris
    Analog IC design automation. I. Automated circuit generation: new concepts and methods. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:2, pp:218-238 [Journal]
  10. Costas A. Makris, Christofer Toumazou
    Analog IC design automation. II. Automated circuit correction by qualitative reasoning. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:2, pp:239-254 [Journal]
  11. Irith Pomeranz, Sudhakar M. Reddy
    On correction of multiple design errors. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:2, pp:255-264 [Journal]
  12. Ting-Chi Wang, Martin D. F. Wong, Yachyang Sun, Chak-Kuen Wong
    Optimal net assignment. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:2, pp:265-269 [Journal]
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