Journals in DBLP

IEEE Trans. on CAD of Integrated Circuits and Systems
1995, volume: 14, number: 3

1. Ching-Yi Wang, Keshab K. Parhi
   High-level DSP synthesis using concurrent transformations, scheduling, and allocation. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:3, pp:274-295 [Journal]
   
2. Moon-Jung Chung, Sangchul Kim
   A path-oriented algorithm for the cell selection problem. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:3, pp:296-307 [Journal]
   
3. Weitong Chuang, Sachin S. Sapatnekar, Ibrahim N. Hajj
   Timing and area optimization for standard-cell VLSI circuit design. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:3, pp:308-320 [Journal]
   
4. Jason Cong, Kwok-Shing Leung
   Optimal wiresizing under Elmore delay model. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:3, pp:321-336 [Journal]
   
5. Wen-Chung Kao, Tai-Ming Parng
   Cross point assignment with global rerouting for general-architecture designs. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:3, pp:337-348 [Journal]
   
6. Wern-Jieh Sun, Carl Sechen
   Efficient and effective placement for very large circuits. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:3, pp:349-359 [Journal]
   
7. Michael M. Green, Alan N. Willson Jr.
   An algorithm for identifying unstable operating points using SPICE. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:3, pp:360-370 [Journal]
   
8. Ching-Dong Chen, Yuh-Sheng Lee, Allen C.-H. Wu, Youn-Long Lin
   TRACER-fpga: a router for RAM-based FPGA's. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:3, pp:371-374 [Journal]
   
9. Wen-Ben Jone, Christos A. Papachristou
   A coordinated circuit partitioning and test generation method for pseudo-exhaustive testing of VLSI circuits. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:3, pp:374-384 [Journal]
   
10. Ayman I. Kayssi, Karem A. Sakallah
    Timing models for gallium arsenide direct-coupled FET logic circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:3, pp:384-393 [Journal]
    
11. Yu-Wen Tsay, Youn-Long Lin
    A row-based cell placement method that utilizes circuit structural properties. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:3, pp:393-397 [Journal]