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Journals in DBLP

IEEE Trans. on CAD of Integrated Circuits and Systems
2002, volume: 21, number: 3

  1. Chunhong Chen, Xiaojian Yang, Majid Sarrafzadeh
    Predicting potential performance for digital circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:3, pp:253-262 [Journal]
  2. Feodor F. Dragan, Andrew B. Kahng, Ion I. Mandoiu, Sudhakar Muddu, Alexander Zelikovsky
    Provably good global buffering by generalized multiterminalmulticommodity flow approximation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:3, pp:263-274 [Journal]
  3. Sung Tae Jung, Chris J. Myers
    Direct synthesis of timed circuits from free-choice STGs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:3, pp:275-290 [Journal]
  4. Dinesh Ramanathan, Sandy Irani, Rajesh K. Gupta
    An analysis of system level power management algorithms and theireffects on latency. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:3, pp:291-305 [Journal]
  5. Qi Wang, Sarma B. K. Vrudhula
    Algorithms for minimizing standby power in deep submicrometer, dual-Vt CMOS circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:3, pp:306-318 [Journal]
  6. Jason Cong, David Zhigang Pan
    Wire width planning for interconnect performance optimization. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:3, pp:319-329 [Journal]
  7. Weiping Shi, Jianguo Liu, Naveen Kakani, Tiejun Yu
    A fast hierarchical algorithm for three-dimensional capacitanceextraction. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:3, pp:330-336 [Journal]
  8. Akio Ushida, Yoshihiro Yamagami, Yoshifumi Nishio, Ikkei Kinouchi, Yasuaki Inoue
    An efficient algorithm for finding multiple DC solutions based onthe SPICE-oriented Newton homotopy method. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:3, pp:337-348 [Journal]
  9. Pramodchandran N. Variyam, Sasikumar Cherubal, Abhijit Chatterjee
    Prediction of analog performance parameters using fast transienttesting. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:3, pp:349-361 [Journal]
  10. Hiroshi Takahashi, Kwame Osei Boateng, Kewal K. Saluja, Yuzo Takamatsu
    On diagnosing multiple stuck-at faults using multiple and singlefault simulation in combinational circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:3, pp:362-368 [Journal]
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The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
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