Journals in DBLP

IEEE Trans. on CAD of Integrated Circuits and Systems
1993, volume: 12, number: 1

1. Nishit P. Parikh, Chi-Yuan Lo, Anoop Singhal, Kwok W. Wu
   HS: a hierarchical search package for CAD data. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:1, pp:1-5 [Journal]
   
2. Masahiro Fujita, Hisanori Fujisawa, Yusuke Matsunaga
   Variable ordering algorithms for ordered binary decision diagrams and their evaluation. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:1, pp:6-12 [Journal]
   
3. Kwang-Ting Cheng
   Redundancy removal for sequential circuits without reset states. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:1, pp:13-24 [Journal]
   
4. Derek C. Wong, Giovanni De Micheli, Michael J. Flynn
   Designing high-performance digital circuits using wave pipelining: algorithms and practical experiences. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:1, pp:25-46 [Journal]
   
5. Carlo H. Séquin, Heloisa da Silva Facanha
   Corner-stitched tiles with curved boundaries [circuit layout]. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:1, pp:47-58 [Journal]
   
6. Kjell O. Jeppson, Sven Christensson, Nils Hedenstierna
   Formal definitions of edge-based geometric design rules. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:1, pp:59-69 [Journal]
   
7. Jason Cong, Moazzem Hossain, Naveed A. Sherwani
   A provably good multilayer topological planar routing algorithm in IC layout designs. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:1, pp:70-78 [Journal]
   
8. Vwani P. Roychowdhury, Jonathan W. Greene, Abbas El Gamal
   Segmented channel routing. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:1, pp:79-95 [Journal]
   
9. Shiuh-Wuu Lee
   A proposed method for determining a MOSFET gate electrode's bottom dimension and the on-state fringing capacitance. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:1, pp:96-101 [Journal]
   
10. Benjamin R. Epstein, Martin H. Czigler, Steven R. Miller
    Fault detection and classification in linear integrated circuits: an application of discrimination analysis and hypothesis testing. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:1, pp:102-113 [Journal]
    
11. Niraj K. Jha, Abha Ahuja
    Easily testable nonrestoring and restoring gate-level cellular array dividers. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:1, pp:114-123 [Journal]
    
12. Pinaki Mazumder, Jih-Shyr Yih
    A new built-in self-repair approach to VLSI memory yield enhancement by using neural-type circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:1, pp:124-136 [Journal]
    
13. Fadi Maamari, Janusz Rajski
    The dynamic reduction of fault simulation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:1, pp:137-148 [Journal]
    
14. Wen-Ben Jone, Patrick H. Madden
    Multiple fault testing using minimal single fault test set for fanout-free circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:1, pp:149-157 [Journal]
    
15. Hervé J. Touati, Robert K. Brayton
    Computing the initial states of retimed circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:1, pp:157-162 [Journal]
    
16. Alan Rotman, Ran Ginosar
    Control unit synthesis from a high-level language. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:1, pp:162-167 [Journal]
    
17. Kyunrak Chong, Sartaj Sahni
    Minimizing total wire length by flipping modules. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:1, pp:167-175 [Journal]
    
18. Jan-Ming Ho, Atsushi Suzuki, Majid Sarrafzadeh
    An exact algorithm for single-layer wire length minimization. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:1, pp:175-180 [Journal]
    
19. Nils Hedenstierna, Kjell O. Jeppson
    Comments on `A module generator for optimized CMOS buffers'. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:1, pp:180-181 [Journal]