D. L. Springer, Donald E. Thomas Exploiting the special structure of conflict and compatibility graphs in high-level synthesis. [Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:7, pp:843-856 [Journal]
June-Kyung Rho, Fabio Somenzi Don't care sequences and the optimization of interacting finite state machines. [Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:7, pp:865-874 [Journal]
Shun-Shii Lin Constant-time algorithms for the channel assignment problem on processor arrays with reconfigurable bus systems. [Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:7, pp:884-890 [Journal]
Xiaoyu Song, Xuehou Tan An optimal channel-routing algorithm in the times square model. [Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:7, pp:891-898 [Journal]
Rochit Rajsuman A new testing method for EEPLA. [Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:7, pp:935-939 [Journal]
Jos van Sas, Francky Catthoor, Hugo De Man Cellular automata based deterministic self-test strategies for programmable data paths. [Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:7, pp:940-949 [Journal]
Sharad Malik Analysis of cyclic combinational circuits. [Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:7, pp:950-956 [Journal]
NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP