Journals in DBLP

IEEE Trans. on CAD of Integrated Circuits and Systems
1992, volume: 11, number: 9

1. Fur-Shing Tsai, Yu-Chin Hsu
   STAR: An automatic data path allocator. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:9, pp:1053-1064 [Journal]
   
2. Kwang-Ting Cheng, Jing-Yang Jou
   A functional fault model for sequential machines. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:9, pp:1065-1073 [Journal]
   
3. Lars W. Hagen, Andrew B. Kahng
   New spectral methods for ratio cut partitioning and clustering. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:9, pp:1074-1085 [Journal]
   
4. Xiaodong Zhang
   Dynamic and static load balancing for solving block bordered circuit equations on multiprocessors. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:9, pp:1086-1094 [Journal]
   
5. Majid Sarrafzadeh, Chak-Kuen Wong
   Hierarchical Steiner tree construction in uniform orientations. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:9, pp:1095-1103 [Journal]
   
6. Tsuneo Okubo, Takashi Watanabe, Kou Wada, Kazuyuki Saito
   A novel geometric resizing technique for data conversion from CAD data to electron beam exposure data. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:9, pp:1104-1113 [Journal]
   
7. Masayoshi Shirahata, Hiromi Kusano, Norihiko Kotani, Shigeru Kusanoki, Yoichi Akasaka
   A mobility model including the screening effect in MOS inversion layer. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:9, pp:1114-1119 [Journal]
   
8. Peter M. Maurer
   Two new techniques for unit-delay compiled simulation. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:9, pp:1120-1130 [Journal]
   
9. Larry G. Jones
   An incremental zero/integer delay switch-level simulation environment. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:9, pp:1131-1139 [Journal]
   
10. Mark Hirsch, Daniel P. Siewiorek
    The effect of placement of automatically extracted structure. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:9, pp:1140-1152 [Journal]
    
11. Weiping Shi, W. Kent Fuchs
    Probabilistic analysis and algorithms for reconfiguration of memory arrays. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:9, pp:1153-1160 [Journal]
    
12. Wu-Tung Cheng, James L. Lewandowski, Eleanor Wu
    Optimal diagnostic methods for wiring interconnects. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:9, pp:1161-1166 [Journal]
    
13. Abhijit Ghosh, Srinivas Devadas, A. Richard Newton
    Heuristic minimization of Boolean relations using testing techniques. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:9, pp:1166-1172 [Journal]