Carl Pixley A theory and implementation of sequential hardware equivalence. [Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:12, pp:1469-1478 [Journal]
Richard W. Thaik, Ngee Lek, Sung-Mo Kang A new global router using zero-one integer linear programming techniques for sea-of-gates and custom logic arrays. [Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:12, pp:1479-1494 [Journal]
Jin-fuw Lee, Chak-Kuen Wong A performance-aimed cell compactor with automatic jogs. [Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:12, pp:1495-1507 [Journal]
Shan-Ping Chin, Ching-Yuan Wu A new methodology for two-dimensional numerical simulation of semiconductor devices. [Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:12, pp:1508-1521 [Journal]
H.-C. Chow, W.-S. Feng, James B. Kuo An improved analytical short-channel MOSFET model valid in all regions of operating for analog/digital circuit simulation. [Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:12, pp:1522-1528 [Journal]
Shiu-Kai Chin Verified functions for generating signed-binary arithmetic hardware. [Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:12, pp:1529-1558 [Journal]
Srinivas Devadas, Kurt Keutzer Validatable nonrobust delay-fault testable circuits via logic synthesis. [Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:12, pp:1559-1573 [Journal]
