Journals in DBLP

IEEE Trans. on CAD of Integrated Circuits and Systems
1998, volume: 17, number: 9

1. Jason Cong, Chang Wu
   An efficient algorithm for performance-optimal FPGA technology mapping with retiming. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:9, pp:738-748 [Journal]
   
2. Alex Kondratyev, Michael Kishinevsky, Alexandre Yakovlev
   Hazard-free implementation of speed-independent circuits. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:9, pp:749-771 [Journal]
   
3. Feng Wang, Donald L. Dietmeyer
   Exploiting near symmetry in multilevel logic synthesis. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:9, pp:772-781 [Journal]
   
4. Kenneth Y. Yun, Bill Lin, David L. Dill, Srinivas Devadas
   BDD-based synthesis of extended burst-mode controllers. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:9, pp:782-792 [Journal]
   
5. Jun Dong Cho, Majid Sarrafzadeh
   Four-bend top-down global routing. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:9, pp:793-802 [Journal]
   
6. Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
   Maple-opt: a performance-oriented simultaneous technology mapping, placement, and global routing algorithm for FPGAs. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:9, pp:803-818 [Journal]
   
7. Asawaree Kalavade, P. A. Subrahmanyam
   Hardware/software partitioning for multifunction systems. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:9, pp:819-837 [Journal]
   
8. Chih-Chang Lin, Malgorzata Marek-Sadowska, Kwang-Ting Cheng, Mike Tien-Chien Lee
   Test-point insertion: scan paths through functional logic. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:9, pp:838-851 [Journal]
   
9. Chih-Chang Lin, Malgorzata Marek-Sadowska, Mike Tien-Chien Lee, Kuang-Chien Chen
   Cost-free scan: a low-overhead scan path design. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:9, pp:852-861 [Journal]
   
10. Zhihua Wang, Georges G. E. Gielen, Willy M. C. Sansen
    Probabilistic fault detection and the selection of measurements for analog integrated circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:9, pp:862-872 [Journal]
    
11. Marwan A. Gharaybeh, Michael L. Bushnell, Vishwani D. Agrawal
    A parallel-vector concurrent-fault simulator and generation of single-input-change tests for path-delay faults. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:9, pp:873-876 [Journal]
    
12. Yiming Gong, Sreejit Chakravarty
    Locating bridging faults using dynamically computed stuck-at fault dictionaries. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:9, pp:876-887 [Journal]