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Journals in DBLP

IEEE Trans. on CAD of Integrated Circuits and Systems
2002, volume: 21, number: 1

  1. Yih-Chih Chou, Youn-Long Lin
    Effective enforcement of path-delay constraints inperformance-driven placement. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:1, pp:15-22 [Journal]
  2. Padmini Gopalakrishnan, Altan Odabasioglu, Lawrence T. Pileggi, Salil Raje
    An analysis of the wire-load model uncertainty problem. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:1, pp:23-31 [Journal]
  3. Jinan Lou, Shashidhar Thakur, Shankar Krishnamoorthy, Henry S. Sheng
    Estimating routing congestion using probabilistic analysis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:1, pp:32-41 [Journal]
  4. Shigetoshi Nakatake, Yukiko Kubo, Yoji Kajitani
    Consistent floorplanning with hierarchical superconstraints. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:1, pp:42-49 [Journal]
  5. Ankireddy Nalamalpu, Sriram Srinivasan, Wayne P. Burleson
    Boosters for driving long onchip interconnects - design issues, interconnect synthesis, and comparison with repeaters. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:1, pp:50-62 [Journal]
  6. Ruiqi Tian, Xiaoping Tang, Martin D. F. Wong
    Dummy-feature placement for chemical-mechanical polishinguniformity in a shallow-trench isolation process. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:1, pp:63-71 [Journal]
  7. Xiaojian Yang, Ryan Kastner, Majid Sarrafzadeh
    Congestion estimation during top-down placement. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:1, pp:72-80 [Journal]
  8. Shiyou Zhao, Kaushik Roy, Cheng-Kok Koh
    Decoupling capacitance allocation and its application topower-supply noise-aware floorplanning. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:1, pp:81-92 [Journal]
  9. Sabyasachi Das, Sunil P. Khatri
    An efficient and regular routing methodology for datapath designsusing net regularity extraction. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:1, pp:93-101 [Journal]
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The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
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