Journals in DBLP

IEEE Trans. on CAD of Integrated Circuits and Systems
1995, volume: 14, number: 4

1. Prabir C. Maulik, L. Richard Carley, Rob A. Rutenbar
   Integer programming based topology selection of cell-level analog circuits. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:4, pp:401-412 [Journal]
   
2. Scott Hazelhurst, Carl-Johan H. Seger
   A simple theorem prover based on symbolic trajectory evaluation and BDD's. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:4, pp:413-422 [Journal]
   
3. Malgorzata Marek-Sadowska, Majid Sarrafzadeh
   The crossing distribution problem [IC layout]. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:4, pp:423-433 [Journal]
   
4. Kazuhiro Takahashi, Kazuo Nakajima, Masayuki Terai, Koji Sato
   Min-cut placement with global objective functions for large scale sea-of-gates arrays. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:4, pp:434-446 [Journal]
   
5. Michael S. Obrecht, Mohamed I. Elmasry, Edwin L. Heasell
   TRASIM: compact and efficient two-dimensional transient simulator for arbitrary planar semiconductor devices. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:4, pp:447-458 [Journal]
   
6. Jacco L. Pleumeekers, Claude M. Simon, Serge Mottet
   Investigation into the properties of the explicit method for the resolution of the semiconductor device equations. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:4, pp:459-463 [Journal]
   
7. Asim Salim, Tajinder Manku, Arokia Nathan
   Modeling of magnetic field sensitivity of bipolar magnetotransistors using HSPICE. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:4, pp:464-469 [Journal]
   
8. Umakanta Choudhury, Alberto L. Sangiovanni-Vincentelli
   Automatic generation of analytical models for interconnect capacitances. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:4, pp:470-480 [Journal]
   
9. Abhijit Dharchoudhury, Sung-Mo Kang
   Worst-case analysis and optimization of VLSI circuit performances. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:4, pp:481-492 [Journal]
   
10. Edward W. Y. Liu, Alberto L. Sangiovanni-Vincentelli
    Verification of Nyquist data converters using behavioral simulation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:4, pp:493-502 [Journal]
    
11. Timothy Kam, P. A. Subrahmanyam
    Comparing layouts with HDL models: a formal verification technique. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:4, pp:503-509 [Journal]
    
12. Wen Fang, M. Ebrahim Mokari-Bolhassan, David Smart
    Robust VLSI circuit simulation techniques based on overlapped waveform relaxation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:4, pp:510-518 [Journal]
    
13. Wing Ning Li
    The complexity of segmented channel routing. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:4, pp:518-523 [Journal]
    
14. So-Zen Yao, Chung-Kuan Cheng, Debaprosad Dutt, Surendra Nahar, Chi-Yuan Lo
    A cell-based hierarchical pitchmatching compaction using minimal LP. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:4, pp:523-526 [Journal]