Journals in DBLP

IEEE Trans. on CAD of Integrated Circuits and Systems
1986, volume: 5, number: 1

1. Ping Yang, Dale E. Hocevar, Paul F. Cox, Charles F. Machala III, Pallab K. Chatterjee
   An Integrated and Efficient Approach for MOS VLSI Statistical Circuit Design. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1986, v:5, n:1, pp:5-14 [Journal]
   
2. Norm Herr, John J. Barnes
   Statistical Circuit Simulation Modeling of CMOS VLSI. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1986, v:5, n:1, pp:15-22 [Journal]
   
3. M. L. Stein
   An Efficient Method of Sampling for Statistical Circuit Design. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1986, v:5, n:1, pp:23-29 [Journal]
   
4. M. A. Styblinski
   Problems of Yield Gradient Estimation for Truncated Probability Density Functions. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1986, v:5, n:1, pp:30-38 [Journal]
   
5. Darrell Makarenko, John Tartar
   A Statistical Analysis of PLA Folding. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1986, v:5, n:1, pp:39-51 [Journal]
   
6. Sarma Sastry, Alice C. Parker
   Stochastic Models for Wireability Analysis of Gate Arrays. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1986, v:5, n:1, pp:52-65 [Journal]
   
7. Costas J. Spanos, Stephen W. Director
   Parameter Extraction for Statistical IC Process Characterization. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1986, v:5, n:1, pp:66-78 [Journal]
   
8. M. A. Styblinski, Leszek J. Opalski
   Algorithms and Software Tools for IC Yield Optimization Based on Fundamental Fabrication Parameters. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1986, v:5, n:1, pp:79-89 [Journal]
   
9. J. P. Spoto, W. T. Coston, C. Paul Hernandez
   Statistical Integrated Circuit Design and Characterization. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1986, v:5, n:1, pp:90-103 [Journal]
   
10. Sani R. Nassif, Andrzej J. Strojwas, Stephen W. Director
    A Methodology for Worst-Case Analysis of Integrated Circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1986, v:5, n:1, pp:104-113 [Journal]
    
11. Wojciech Maly, Andrzej J. Strojwas, Stephen W. Director
    VLSI Yield Prediction and Estimation: A Unified Framework. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1986, v:5, n:1, pp:114-130 [Journal]
    
12. David C. Riley, Alberto L. Sangiovanni-Vincentelli
    Models for a New Profit-Based Methodology for Statistical Design of Integrated Circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1986, v:5, n:1, pp:131-169 [Journal]
    
13. Shui-Jinn Wang, Jau-Yien Lee, Chun-Yen Chang
    An Efficient and Reliable Approach for Semiconductor Device Parameter Extraction. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1986, v:5, n:1, pp:170-179 [Journal]
    
14. Kung-Chao Chu, John P. Fishburn, Peter Honeyman, Y. Edmund Lien
    A Database-Driven VLSI Design System. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1986, v:5, n:1, pp:180-187 [Journal]
    
15. Tzu-Mu Lin, Carver Mead
    A Hierarchical Timing Simulation Model. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1986, v:5, n:1, pp:188-197 [Journal]
    
16. Richard C. Jaeger
    Computer-Aided Design of One-Dimensional MOSFET Impurity Profiles. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1986, v:5, n:1, pp:198-203 [Journal]
    
17. Wieslaw Kuzmicz
    Modeling of Minority Carrier Current in Heavily Doped Regions of Bipolar Regions. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1986, v:5, n:1, pp:204-214 [Journal]
    
18. R. H. Uebbing, Masao Fukuma
    Process-Based Three-Dimensional Capacitance Simulation -- TRICEPS. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1986, v:5, n:1, pp:215-220 [Journal]
    
19. J. W. Greene, Kenneth J. Supowit
    Simulated Annealing Without Rejected Moves. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1986, v:5, n:1, pp:221-228 [Journal]
    
20. Michel Dagenais, Vinod K. Agarwal, Nicholas C. Rumin
    McBOOLE: A New Procedure for Exact Logic Minimization. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1986, v:5, n:1, pp:229-238 [Journal]
    
21. Giovanni De Micheli, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
    Correction to "Optimal State Assignment for Finite State Machines". [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1986, v:5, n:1, pp:239-239 [Journal]