Journals in DBLP

IEEE Trans. on CAD of Integrated Circuits and Systems
1998, volume: 17, number: 11

1. Enrico Macii, Massoud Pedram, Fabio Somenzi
   High-level power modeling, estimation, and optimization. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:11, pp:1061-1079 [Journal]
   
2. Cheng-Ta Hsieh, Massoud Pedram
   Microprocessor power estimation using profile-driven program synthesis. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:11, pp:1080-1089 [Journal]
   
3. S. Turgis, Daniel Auvergne
   A novel macromodel for power estimation in CMOS structures. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:11, pp:1090-1098 [Journal]
   
4. Chih-Shun Ding, Chi-Ying Tsui, Massoud Pedram
   Gate-level power estimation using tagged probabilistic simulation. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:11, pp:1099-1107 [Journal]
   
5. Enric Pastor, Jordi Cortadella, Alex Kondratyev, Oriol Roig
   Structural methods for the synthesis of speed-independent circuits. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:11, pp:1108-1129 [Journal]
   
6. Michael Theobald, Steven M. Nowick
   Fast heuristic and exact algorithms for two-level hazard-free logic minimization. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:11, pp:1130-1147 [Journal]
   
7. Rui Martins, Wolfgang Pyka, Rainer Sabelka, Siegfried Selberherr
   High-precision interconnect analysis. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:11, pp:1148-1159 [Journal]
   
8. Mahesh B. Patil
   New discretization scheme for two-dimensional semiconductor device simulation on triangular grid. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:11, pp:1160-1165 [Journal]
   
9. Chris C. N. Chu, Martin D. F. Wong
   A matrix synthesis approach to thermal placement. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:11, pp:1166-1174 [Journal]
   
10. Hannah Honghua Yang, Martin D. F. Wong
    Optimal min-area min-cut replication in partitioned circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:11, pp:1175-1183 [Journal]
    
11. Michael Kishinevsky, Alex Kondratyev, Luciano Lavagno, Alexander Saldanha, Alexander Taubin
    Partial-scan delay fault testing of asynchronous circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:11, pp:1184-1199 [Journal]
    
12. Haluk Konuk, F. Joel Ferguson
    Oscillation and sequential behavior caused by opens in the routing in digital CMOS circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:11, pp:1200-1210 [Journal]
    
13. Radomir S. Stankovic
    Some remarks on terminology in spectral techniques for logic design: Walsh transform and Hadamard matrices. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:11, pp:1211-1214 [Journal]