Journals in DBLP

IEEE Trans. on CAD of Integrated Circuits and Systems
2002, volume: 21, number: 9

1. Mariagiovanna Sami, Donatella Sciuto, Cristina Silvano, Vittorio Zaccaria
   An instruction-level energy model for embedded VLIW architectures. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:9, pp:998-1010 [Journal]
   
2. Piet Vanassche, Georges G. E. Gielen, Willy M. C. Sansen
   Symbolic modeling of periodically time-varying systems usingharmonic transfer matrices. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:9, pp:1011-1024 [Journal]
   
3. Jiang Hu, Sachin S. Sapatnekar
   A timing-constrained simultaneous global routing algorithm. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:9, pp:1025-1036 [Journal]
   
4. Tat Kee Tan, Anand Raghunathan, Ganesh Lakshminarayana, Niraj K. Jha
   High-level energy macromodeling of embedded software. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:9, pp:1037-1050 [Journal]
   
5. Eui-Young Chung, Luca Benini, Giovanni De Micheli, Gabriele Luculli, Marco Carilli
   Value-sensitive automatic code specialization for embedded software. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:9, pp:1051-1067 [Journal]
   
6. Irith Pomeranz
   On the use of random limited-scan to improve at-speed randompattern testing of scan circuits. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:9, pp:1068-1076 [Journal]
   
7. Kaijie Wu, Ramesh Karri
   Algorithm level recomputing using allocation diversity: a registertransfer level approach to time redundancy-based concurrent errordetection. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:9, pp:1077-1087 [Journal]
   
8. Vikram Iyengar, Krishnendu Chakrabarty
   System-on-a-chip test scheduling with precedence relationships, preemption, and power constraints. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:9, pp:1088-1094 [Journal]
   
9. Dimitrios Kagaris, Spyros Tragoudas
   On the nonenumerative path delay fault simulation problem. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:9, pp:1095-1101 [Journal]
   
10. Mutsumi Kimura, Satoshi Inoue, Tatsuya Shimoda
    Table look-up model of thin-film transistors for circuit simulationusing spline interpolation with transformation by y=x+log(x). [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:9, pp:1101-1104 [Journal]
    
11. Dong Xiang, Hideo Fujiwara
    Handling the pin overhead problem of DFTs for high-quality and at-speed tests. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:9, pp:1105-1113 [Journal]