Journals in DBLP

IEEE Trans. on CAD of Integrated Circuits and Systems
1992, volume: 11, number: 8

1. Maciej J. Ciesielski, Seiyang Yang
   PLADE: a two-stage PLA decomposition. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:8, pp:943-954 [Journal]
   
2. Rajiv Jain, Alice C. Parker, Nohbyung Park
   Predicting system-level area and delay for pipelined and nonpipelined designs. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:8, pp:955-965 [Journal]
   
3. Albert V. Ferris-Prabhu
   On the assumptions contained in semiconductor yield models. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:8, pp:966-975 [Journal]
   
4. Chia-Chun Tsai, Sao-Jie Chen, Wu-Shiung Feng
   An H-V alternating router. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:8, pp:976-991 [Journal]
   
5. Ting-Chi Wang, Martin D. F. Wong
   Optimal floorplan area optimization. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:8, pp:992-1002 [Journal]
   
6. Kartikeya Mayaram, Donald O. Pederson
   Coupling algorithms for mixed-level circuit and device simulation. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:8, pp:1003-1012 [Journal]
   
7. Mamoru Kurata, Shin Nakamura
   An explicit method of numerical integration for the complete set of semiconductor device equations. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:8, pp:1013-1023 [Journal]
   
8. Yeong-Yil Yang, Chong-Min Kyung
   HALO: an efficient global placement strategy for standard cells. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:8, pp:1024-1031 [Journal]
   
9. Richard Griffith, Michel S. Nakhla
   Mixed frequency/time domain analysis of nonlinear circuits. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:8, pp:1032-1043 [Journal]
   
10. Somchai Prasitjutrakul, William J. Kubitz
    A performance-driven global router for custom VLSI chip design. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:8, pp:1044-1051 [Journal]