Journals in DBLP

IEEE Trans. on CAD of Integrated Circuits and Systems
1990, volume: 9, number: 4

1. Daniel Weise
   Multilevel verification of MOS circuits. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1990, v:9, n:4, pp:341-351 [Journal]
   
2. Lawrence T. Pillage, Ronald A. Rohrer
   Asymptotic waveform evaluation for timing analysis. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1990, v:9, n:4, pp:352-366 [Journal]
   
3. An-Chang Deng, Yan-Chyuan Shiau
   Generic linear RC delay modeling for digital CMOS circuits. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1990, v:9, n:4, pp:367-376 [Journal]
   
4. San-Yuan Wu, Sartaj Sahni
   Covering rectilinear polygons by rectangles. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1990, v:9, n:4, pp:377-388 [Journal]
   
5. Kurt Mehlhorn, Wolfgang Rülling
   Compaction on the torus [VLSI layout]. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1990, v:9, n:4, pp:389-397 [Journal]
   
6. James P. Cohoon, Dana S. Richards, Jeffrey S. Salowe
   An optimal Steiner tree algorithm for a net whose terminals lie on the perimeter of a rectangle. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1990, v:9, n:4, pp:398-407 [Journal]
   
7. Jason Cong, C. L. Liu
   Over-the-cell channel routing. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1990, v:9, n:4, pp:408-418 [Journal]
   
8. Jan-Ming Ho, Majid Sarrafzadeh, Gopalakrishnan Vijayan, Chak-Kuen Wong
   Pad minimization for planar routing of multiple power nets. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1990, v:9, n:4, pp:419-426 [Journal]
   
9. K. Iwasaki, F. Arakawa
   An analysis of the aliasing probability of multiple-input signature registers in the case of a 2^m-ary symmetric channel. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1990, v:9, n:4, pp:427-438 [Journal]
   
10. Farid N. Najm, Richard Burch, Ping Yang, Ibrahim N. Hajj
    Probabilistic simulation for reliability analysis of CMOS VLSI circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1990, v:9, n:4, pp:439-450 [Journal]