Journals in DBLP
Daniel Weise Multilevel verification of MOS circuits. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 1990, v:9, n:4, pp:341-351 [Journal ] Lawrence T. Pillage , Ronald A. Rohrer Asymptotic waveform evaluation for timing analysis. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 1990, v:9, n:4, pp:352-366 [Journal ] An-Chang Deng , Yan-Chyuan Shiau Generic linear RC delay modeling for digital CMOS circuits. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 1990, v:9, n:4, pp:367-376 [Journal ] San-Yuan Wu , Sartaj Sahni Covering rectilinear polygons by rectangles. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 1990, v:9, n:4, pp:377-388 [Journal ] Kurt Mehlhorn , Wolfgang Rülling Compaction on the torus [VLSI layout]. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 1990, v:9, n:4, pp:389-397 [Journal ] James P. Cohoon , Dana S. Richards , Jeffrey S. Salowe An optimal Steiner tree algorithm for a net whose terminals lie on the perimeter of a rectangle. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 1990, v:9, n:4, pp:398-407 [Journal ] Jason Cong , C. L. Liu Over-the-cell channel routing. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 1990, v:9, n:4, pp:408-418 [Journal ] Jan-Ming Ho , Majid Sarrafzadeh , Gopalakrishnan Vijayan , Chak-Kuen Wong Pad minimization for planar routing of multiple power nets. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 1990, v:9, n:4, pp:419-426 [Journal ] K. Iwasaki , F. Arakawa An analysis of the aliasing probability of multiple-input signature registers in the case of a 2m -ary symmetric channel. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 1990, v:9, n:4, pp:427-438 [Journal ] Farid N. Najm , Richard Burch , Ping Yang , Ibrahim N. Hajj Probabilistic simulation for reliability analysis of CMOS VLSI circuits. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 1990, v:9, n:4, pp:439-450 [Journal ]