Journals in DBLP

IEEE Trans. on CAD of Integrated Circuits and Systems
2004, volume: 23, number: 3

1. Rafael Escovar, Roberto Suaya
   Optimal design of clock trees for multigigahertz applications. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:3, pp:329-345 [Journal]
   
2. Jason Cong, Sung Kyu Lim
   Edge separability-based circuit clustering with application to multilevel circuit partitioning. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:3, pp:346-357 [Journal]
   
3. Tong Jing, Xianlong Hong, Jingyu Xu, Haiyun Bao, Chung-Kuan Cheng, Jun Gu
   UTACO: a unified timing and congestion optimization algorithm for standard cell global routing. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:3, pp:358-365 [Journal]
   
4. Jinjun Xiong, Lei He
   Full-chip routing optimization with RLC crosstalk budgeting. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:3, pp:366-377 [Journal]
   
5. Sheng Uei Guan, Shu Zhang, Marie Therese Quieta
   2-D CA variation with asymmetric neighborship for pseudorandom number generation. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:3, pp:378-388 [Journal]
   
6. Georges G. E. Gielen, Kenneth Francken, Ewout Martens, Martin Vogels
   An analytical integration method for the simulation of continuous-time /spl Delta//spl Sigma/ modulators. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:3, pp:389-399 [Journal]
   
7. Olaf Schenk, Stefan Röllin, Anshul Gupta
   The effects of unsymmetric matrix permutations and scalings in semiconductor device and circuit simulation. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:3, pp:400-411 [Journal]
   
8. Jun Yuan, Adnan Aziz, Carl Pixley, Ken Albin
   Simplifying Boolean constraint solving for random simulation-vector generation. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:3, pp:412-420 [Journal]
   
9. Subhasish Mitra, Kee Sup Kim
   X-compact: an efficient response compaction technique. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:3, pp:421-432 [Journal]
   
10. Sujit T. Zachariah, Sreejit Chakravarty
    Extraction of two-node bridges from large industrial circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:3, pp:433-439 [Journal]
    
11. Rolf Drechsler, Junhao Shi, Görschwin Fey
    Synthesis of fully testable circuits from BDDs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:3, pp:440-443 [Journal]
    
12. Frank Liu, Chandramouli V. Kashyap, Charles J. Alpert
    A delay metric for RC circuits based on the Weibull distribution. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:3, pp:443-447 [Journal]