Journals in DBLP

IEEE Trans. on CAD of Integrated Circuits and Systems
2003, volume: 22, number: 6

1. Soha Hassoun, Steven M. Nowick, Leon Stok
   Guest Editorial. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:6, pp:662-664 [Journal]
   
2. Prabhakar Kudva, Andrew Sullivan, William E. Dougherty
   Measurements for structural logic synthesis optimizations. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:6, pp:665-674 [Journal]
   
3. Jordi Cortadella
   Timing-driven logic bi-decomposition. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:6, pp:675-685 [Journal]
   
4. Jie-Hong Roland Jiang, Robert K. Brayton
   On the verification of sequential equivalence. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:6, pp:686-697 [Journal]
   
5. Amit Prakash, Ramakrishna Kotla, Tanmoy Mandal, Adnan Aziz
   A high-performance architecture and BDD-based synthesis methodology for packet classification. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:6, pp:698-709 [Journal]
   
6. Vivek V. Shende, Aditya K. Prasad, Igor L. Markov, John P. Hayes
   Synthesis of reversible logic circuits. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:6, pp:710-722 [Journal]
   
7. Fan Mo, Robert K. Brayton
   PLA-based regular structures and their synthesis. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:6, pp:723-729 [Journal]
   
8. Faran Rafiq, Malgorzata Chrzanowska-Jeske, Hannah Honghua Yang, Marcin Jeske, Naveed A. Sherwani
   Integrated floorplanning with buffer/channel insertion for bus-based designs. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:6, pp:730-741 [Journal]
   
9. H. C. Srinivasaiah, Navakanta Bhat
   Mixed-mode simulation approach to characterize the circuit delay sensitivity to implant dose variations. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:6, pp:742-747 [Journal]
   
10. Tingdong Zhou, Steven L. Dvorak, John L. Prince
    Lossy transmission line simulation based on closed-form triangle impulse responses. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:6, pp:748-755 [Journal]
    
11. Jing-Jia Liou, Angela Krstic, Yi-Min Jiang, Kwang-Ting Cheng
    Modeling, testing, and analysis for delay defects and noise effects in deep submicron devices. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:6, pp:756-769 [Journal]
    
12. Yi Zhao, Sujit Dey
    Fault-coverage analysis techniques of crosstalk in chip interconnects. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:6, pp:770-782 [Journal]
    
13. Paul Theo Gonciari, Bashir M. Al-Hashimi, Nicola Nicolici
    Variable-length input Huffman coding for system-on-a-chip test. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:6, pp:783-796 [Journal]
    
14. Abhijit Jas, Jayabrata Ghosh-Dastidar, Mom-Eng Ng, Nur A. Touba
    An efficient test vector compression scheme using selective Huffman coding. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:6, pp:797-806 [Journal]
    
15. Arlindo L. Oliveira, Rajeev Murgai
    On the problem of gate assignment under different rise and fall delays. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:6, pp:807-814 [Journal]
    
16. Hui Xu, Rob A. Rutenbar, Karem A. Sakallah
    sub-SAT: a formulation for relaxed Boolean satisfiability with applications in routing. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:6, pp:814-820 [Journal]