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Journals in DBLP

IEEE Trans. on CAD of Integrated Circuits and Systems
2002, volume: 21, number: 2

  1. Jordi Cortadella, Michael Kishinevsky, Steven M. Burns, Alex Kondratyev, Luciano Lavagno, Ken S. Stevens, Alexander Taubin, Alexandre Yakovlev
    Lazy transition systems and asynchronous circuit synthesis withrelative timing assumptions. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:2, pp:109-130 [Journal]
  2. Yehea I. Ismail, Eby G. Friedman
    DTT: direct truncation of the transfer function - an alternative tomoment matching for tree structured interconnect. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:2, pp:131-144 [Journal]
  3. Zhaoyun Xing, Russell Kao
    Shortest path search using tiles and piecewise linear costpropagation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:2, pp:145-158 [Journal]
  4. Min Zhao, Rajendran Panda, Sachin S. Sapatnekar, David T. Blaauw
    Hierarchical analysis of power distribution networks. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:2, pp:159-168 [Journal]
  5. Stephen A. Edwards
    An Esterel compiler for large control-dominated systems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:2, pp:169-183 [Journal]
  6. Xun Liu, Marios C. Papaefthymiou, Eby G. Friedman
    Retiming and clock scheduling for digital circuit optimization. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:2, pp:184-203 [Journal]
  7. Khurram Muhammad, Kaushik Roy
    A graph theoretic approach for synthesizing very low-complexityhigh-speed digital filters. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:2, pp:204-216 [Journal]
  8. Said Hamdioui, A. J. van de Goor
    Thorough testing of any multiport memory with linear tests. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:2, pp:217-231 [Journal]
  9. Ki-Wook Kim, Taewhan Kim, C. L. Liu, Sung-Mo Kang
    Domino logic synthesis based on implication graph. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:2, pp:232-240 [Journal]
  10. Patrick H. Madden
    Reporting of standard cell placement results. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:2, pp:240-247 [Journal]
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The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
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