Journals in DBLP

IEEE Trans. on CAD of Integrated Circuits and Systems
1989, volume: 8, number: 11

1. Maurizio Damiani, Piero Olivo, Michele Favalli, Bruno Riccò
   An analytical model for the aliasing probability in signature analysis testing. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1989, v:8, n:11, pp:1133-1144 [Journal]
   
2. Chantal Robach, Daniel Lutoff, Nouar Garcia
   Knowledge-based functional specification of test and maintenance programs. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1989, v:8, n:11, pp:1145-1156 [Journal]
   
3. Anucha Pitaksanonkul, Suchai Thanawastien, Chidchanok Lursinsap
   Comparisons of quad trees and 4-D trees: new results [VLSI layout]. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1989, v:8, n:11, pp:1157-1164 [Journal]
   
4. Chong S. Rim, Toshinobu Kashiwabara, Kazuo Nakajima
   Exact algorithms for multilayer topological via minimization. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1989, v:8, n:11, pp:1165-1173 [Journal]
   
5. Sanjeev Rao Maddila, Dian Zhou
   Routing in general junctions. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1989, v:8, n:11, pp:1174-1184 [Journal]
   
6. Teresa H. Y. Meng, Robert W. Brodersen, David G. Messerschmitt
   Automatic synthesis of asynchronous circuits from high-level specifications. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1989, v:8, n:11, pp:1185-1205 [Journal]
   
7. Srinivas Devadas, A. Richard Newton
   Decomposition and factorization of sequential finite state machines. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1989, v:8, n:11, pp:1206-1217 [Journal]
   
8. Ludo Weyten, Wim De Pauw
   Performance prediction for adaptive quad tree graphical data structures. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1989, v:8, n:11, pp:1218-1222 [Journal]
   
9. Sandip Kundu
   Design of multioutput CMOS combinational logic circuits for robust testability. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1989, v:8, n:11, pp:1222-1226 [Journal]
   
10. Takashi Nanya, Hendrik A. Goosen
    The Byzantine hardware fault model. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1989, v:8, n:11, pp:1226-1231 [Journal]