Journals in DBLP

IEEE Trans. on CAD of Integrated Circuits and Systems
1989, volume: 8, number: 8

1. John R. F. McMacken, Savvas G. Chamberlain
   CHORD: a modular semiconductor device simulation development tool incorporating external network models. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1989, v:8, n:8, pp:826-836 [Journal]
   
2. Rex E. Lowther
   A discretization scheme that allows coarse grid-spacing in finite-difference process simulation. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1989, v:8, n:8, pp:837-841 [Journal]
   
3. Peter D. Hortensius, Robert D. McLeod, Werner Pries, D. M. Miller, Howard C. Card
   Cellular automata-based pseudorandom number generators for built-in self-test. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1989, v:8, n:8, pp:842-859 [Journal]
   
4. Ravi Nair, C. Leonard Berman, Peter S. Hauge, Ellen J. Yoffa
   Generation of performance constraints for layout. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1989, v:8, n:8, pp:860-874 [Journal]
   
5. Shuo Huang, Omar Wing
   Improved gate matrix layout. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1989, v:8, n:8, pp:875-889 [Journal]
   
6. Majid Sarrafzadeh, D. T. Lee
   A new approach to topological via minimization. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1989, v:8, n:8, pp:890-900 [Journal]
   
7. Devadas Varma, E. A. Trachtenberg
   Design automation tools for efficient implementation of logic functions by decomposition. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1989, v:8, n:8, pp:901-916 [Journal]
   
8. Jitender S. Deogun, Bhargab B. Bhattacharya
   Via minimization in VLSI routing with movable terminals. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1989, v:8, n:8, pp:917-920 [Journal]
   
9. José Pineda de Gyvez, Jochen A. G. Jess
   On the design and implementation of a wafer yield editor. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1989, v:8, n:8, pp:920-925 [Journal]
   
10. Wayne Wolf, Kurt Keutzer, Janaki Akella
    Addendum to 'A kernel-finding state assignment algorithm for multi-level logic'. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1989, v:8, n:8, pp:925-927 [Journal]
    
11. George W. Rhyne, Michael Steer, K. S. Kundent, Alberto L. Sangiovanni-Vincentelli
    Comments on 'Simulation of nonlinear circuits in the frequency domain' [with reply]. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1989, v:8, n:8, pp:927-929 [Journal]
    
12. James B. Kuo, G. P. Rosseel, Robert W. Dutton
    Two-dimensional analysis of a merged BiPMOS device. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1989, v:8, n:8, pp:929-932 [Journal]