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Journals in DBLP

IEEE Trans. on CAD of Integrated Circuits and Systems
1998, volume: 17, number: 6

  1. Chih-Shun Ding, Qing Wu, Cheng-Ta Hsieh, Massoud Pedram
    Stratified random sampling for power estimation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:6, pp:465-471 [Journal]
  2. Evguenii I. Goldberg, Tiziano Villa, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
    Theory and algorithms for face hypercube embedding. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:6, pp:472-488 [Journal]
  3. Peichen Pan, Arvind K. Karandikar, C. L. Liu
    Optimal clock period clustering for sequential circuits with retiming. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:6, pp:489-498 [Journal]
  4. Sudip Nag, Rob A. Rutenbar
    Performance-driven simultaneous placement and routing for FPGA's. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:6, pp:499-518 [Journal]
  5. Shigetoshi Nakatake, Kunihiro Fujiyoshi, Hiroshi Murata, Yoji Kajitani
    Module packing based on the BSG-structure and IC layout applications. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:6, pp:519-530 [Journal]
  6. Albrecht P. Stroele, Hans-Joachim Wunderlich
    Hardware-optimal test register insertion. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:6, pp:531-539 [Journal]
  7. Naveena Nagi, Abhijit Chatterjee, Heebyung Yoon, Jacob A. Abraham
    Signature analysis for analog and mixed-signal circuit test response compaction. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:6, pp:540-546 [Journal]
  8. Shangzhi Sun, David Hung-Chang Du, Hsi-Chuan Chen
    Efficient timing analysis for CMOS circuits considering data dependent delays. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:6, pp:546-552 [Journal]
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