The SCEAS System
Navigation Menu

Journals in DBLP

IEEE Trans. on CAD of Integrated Circuits and Systems
1983, volume: 2, number: 3

  1. Takeshi Tokuda, Kaoru Okazaki, K. Sakashita, I. Ohkura, T. Enomoto
    Delay-Time Modeling for ED MOS Logic LSI. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1983, v:2, n:3, pp:129-134 [Journal]
  2. Donald E. Thomas, John A. Nestor
    Defining and Implementing a Multilevel Design Representation with Simulation Applications. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1983, v:2, n:3, pp:135-145 [Journal]
  3. Mark Horowitz, Robert W. Dutton
    Resistance Extraction from Mask Layout Data. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1983, v:2, n:3, pp:145-150 [Journal]
  4. Giovanni De Micheli, Alberto L. Sangiovanni-Vincentelli
    Multiple Constrained Folding of Programmable Logic Arrays: Theory and Applications. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1983, v:2, n:3, pp:151-167 [Journal]
  5. Giovanni De Micheli, A. Richard Newton, Alberto L. Sangiovanni-Vincentelli
    Symmetric Displacement Algorithms for the Timing Analysis of Large Scale Circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1983, v:2, n:3, pp:167-180 [Journal]
  6. Dale E. Hocevar, Michael R. Lightner, Timothy N. Trick
    A Study of Variance Reduction Techniques for Estimating Circuit Yields. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1983, v:2, n:3, pp:180-192 [Journal]
  7. Dundar Dumlugol, Hugo De Man, Piet Stevens, Guido G. Schrooten
    Local Relaxation Algorithms for Event-Driven Simulation of MOS Networks Including Assignable Delay Modeling. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1983, v:2, n:3, pp:193-202 [Journal]
  8. Jorge Rubinstein, Paul Penfield Jr., Mark A. Horowitz
    Signal Delay in RC Tree Networks. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1983, v:2, n:3, pp:202-211 [Journal]
NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002