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Journals in DBLP

IEEE Trans. on CAD of Integrated Circuits and Systems
1999, volume: 18, number: 12

  1. Haris Lekatsas, Wayne Wolf
    SAMC: a code compression algorithm for embedded processors. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:12, pp:1689-1701 [Journal]
  2. Inki Hong, Darko Kirovski, Gang Qu, Miodrag Potkonjak, Mani B. Srivastava
    Power optimization of variable-voltage core-based systems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:12, pp:1702-1714 [Journal]
  3. Kamal S. Khouri, Ganesh Lakshminarayana, Niraj K. Jha
    High-level synthesis of low-power control-flow intensive circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:12, pp:1715-1729 [Journal]
  4. Alfredo J. Piazza, Can E. Korman, Amro M. Jaradeh
    A physics-based semiconductor noise model suitable for efficient numerical implementation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:12, pp:1730-1740 [Journal]
  5. Wolfgang Pyka, Peter Fleischmann, Bernhard Haindl, Siegfried Selberherr
    Three-dimensional simulation of HPCVD-linking continuum transport and reaction kinetics with topography simulation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:12, pp:1741-1749 [Journal]
  6. Alexandre Linhares, Horacio Hideki Yanasse, José Ricardo de Almeida Torreao
    Linear gate assignment: a fast statistical mechanics approach. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:12, pp:1750-1758 [Journal]
  7. Youxin Gao, Martin D. F. Wong
    Wire-sizing optimization with inductance consideration using transmission-line model. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:12, pp:1759-1767 [Journal]
  8. Haluk Konuk
    Voltage- and current-based fault simulation for interconnect open defects. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:12, pp:1768-1779 [Journal]
  9. Kent L. Einspahr, Shashank K. Mehta, Sharad C. Seth
    A synthesis for testability scheme for finite state machines using clock control. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:12, pp:1780-1792 [Journal]
  10. Kuen-Jong Lee, Jih-Jeen Chen, Cheng-Hua Huang
    Broadcasting test patterns to multiple circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:12, pp:1793-1802 [Journal]
  11. Andreas G. Veneris, Ibrahim N. Hajj
    Design error diagnosis and correction via test vector simulation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:12, pp:1803-1816 [Journal]
  12. Ashok Vittal, Lauren Hui Chen, Malgorzata Marek-Sadowska, Kai-Ping Wang, Sherry Yang
    Crosstalk in VLSI interconnections. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:12, pp:1817-1824 [Journal]
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