Journals in DBLP

IEEE Trans. on CAD of Integrated Circuits and Systems
1995, volume: 14, number: 5

1. Miodrag Potkonjak, Sujit Dey, Rabindra K. Roy
   Considering testability at behavioral level: use of transformations for partial scan cost minimization under timing and area constraints. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:5, pp:531-546 [Journal]
   
2. Steffen Tarnick
   Controllable self-checking checkers for conditional concurrent checking. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:5, pp:547-553 [Journal]
   
3. Mody Lempel, Sandeep K. Gupta, Melvin A. Breuer
   Test embedding with discrete logarithms. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:5, pp:554-566 [Journal]
   
4. Siyad C. Ma, Edward J. McCluskey
   Open faults in BiCMOS gates. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:5, pp:567-575 [Journal]
   
5. Wuudiann Ke, Premachandran R. Menon
   Path-delay-fault testable nonscan sequential circuits. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:5, pp:576-582 [Journal]
   
6. Aiman H. El-Maleh, Janusz Rajski
   Delay-fault testability preservation of the concurrent decomposition and factorization transformations. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:5, pp:582-590 [Journal]
   
7. Keerthi Heragu, Vishwani D. Agrawal, Michael L. Bushnell
   Fault coverage estimation by test vector sampling. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:5, pp:590-596 [Journal]
   
8. Terry Lee, Weitong Chuang, Ibrahim N. Hajj, W. Kent Fuchs
   Circuit-level dictionaries of CMOS bridging faults. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:5, pp:596-603 [Journal]
   
9. Peter C. Maxwell
   Reductions in quality caused by uneven fault coverage of different areas of an integrated circuit. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:5, pp:603-607 [Journal]
   
10. Vladimir Kolarik, Salvador Mir, Marcelo Lubaszewski, Bernard Courtois
    Analog checkers with absolute and relative tolerances. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:5, pp:607-612 [Journal]
    
11. Yanbing Xu, Mostafa H. Abd-El-Barr, Carl McCrosky
    Graph-based output phase assignment for PLA minimization. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:5, pp:613-622 [Journal]
    
12. Lung-Tien Liu, Ming-Ter Kuo, Chung-Kuan Cheng, T. C. Hu
    A replication cut for two-way partitioning. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:5, pp:623-630 [Journal]
    
13. Masato Fujinaga, I. Tottori, Tatsuya Kunikiyo, Tetsuya Uchida, Norihiko Kotani, Yasumasa Tsukamoto
    3-D numerical modeling of thermal flow for insulating thin film using surface diffusion. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:5, pp:631-638 [Journal]
    
14. Peter Feldmann, Roland W. Freund
    Efficient linear circuit analysis by Pade approximation via the Lanczos process. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:5, pp:639-649 [Journal]