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Journals in DBLP

IEEE Trans. on CAD of Integrated Circuits and Systems
1992, volume: 11, number: 10

  1. Shinichiro Haruyama, Martin D. F. Wong, Donald S. Fussell
    Topological channel routing [VLSI]. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:10, pp:1177-1197 [Journal]
  2. Kevin S. Eshbaugh
    Generation of correlated parameters for statistical circuit simulation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:10, pp:1198-1206 [Journal]
  3. Bogdan J. Falkowski, Ingo Schäfer, Marek A. Perkowski
    Effective computer methods for the calculation of Rademacher-Walsh spectrum for completely and incompletely specified Boolean functions. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:10, pp:1207-1226 [Journal]
  4. Mark William Kahrs
    Silicon compilation of very high level language. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:10, pp:1227-1246 [Journal]
  5. Hong June Park, Ping Keung Ko, Chenming Hu
    A non-quasi-static MOSFET model for SPICE-AC analysis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:10, pp:1247-1257 [Journal]
  6. Rui Wang, Omar Wing
    Transient analysis of dispersive VLSI interconnects terminated in nonlinear loads. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:10, pp:1258-1277 [Journal]
  7. Abu S. M. Hassan, Vinod K. Agarwal, Benoit Nadeau-Dostie, Janusz Rajski
    BIST of PCB interconnects using boundary-scan architecture. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:10, pp:1278-1288 [Journal]
  8. Sy-Yen Kuo, Ing-Yi Chen
    Efficient reconfiguration algorithms for degradable VLSI/WSI arrays. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:10, pp:1289-1300 [Journal]
  9. Slawomir Pilarski, Andrzej Krasniewski, Tiko Kameda
    Estimating testing effectiveness of the circular self-test path technique. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:10, pp:1301-1316 [Journal]
  10. Uwe Hinsberger, Reiner Kolla
    A cell-based approach to performance optimization of fanout-free circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:10, pp:1317-1322 [Journal]
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