Journals in DBLP

IEEE Trans. on CAD of Integrated Circuits and Systems
1994, volume: 13, number: 8

1. Yung-Te Lai, Massoud Pedram, Sarma B. K. Vrudhula
   EVBDD-based algorithms for integer linear programming, spectral transformation, and function decomposition. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:8, pp:959-975 [Journal]
   
2. J. Narasimham, Kazuo Nakajima, Chong S. Rim, Anton T. Dahbura
   Yield enhancement of programmable ASIC arrays by reconfiguration of circuit placements. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:8, pp:976-986 [Journal]
   
3. C. Thomas Gray, Wentai Liu, Ralph K. Cavin III
   Timing constraints for wave-pipelined systems. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:8, pp:987-1004 [Journal]
   
4. Prabhat Jain, Ganesh Gopalakrishnan
   Efficient symbolic simulation-based verification using the parametric form of Boolean expressions. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:8, pp:1005-1015 [Journal]
   
5. Li-Ren Liu, Hsi-Chuan Chen, David Hung-Chang Du
   The calculation of signal stable ranges in combinational circuits. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:8, pp:1016-1023 [Journal]
   
6. Carl Pixley, Seh-Woong Jeong, Gary D. Hachtel
   Exact calculation of synchronizing sequences based on binary decision diagrams. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:8, pp:1024-1034 [Journal]
   
7. Gwo-Chung Tai, Can E. Korman, Isaak D. Mayergoyz
   A parallel-in-time method for the transient simulation of SOI devices with drain current overshoots. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:8, pp:1035-1044 [Journal]
   
8. Wing Ning
   Strongly NP-hard discrete gate-sizing problems. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:8, pp:1045-1051 [Journal]
   
9. Elizabeth M. Rudnick, Vivek Chickermane, Janak H. Patel
   An observability enhancement approach for improved testability and at-speed test. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:8, pp:1051-1056 [Journal]
   
10. Jacob Savir, Srinivas Patil
    Broad-side delay test. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:8, pp:1057-1064 [Journal]
    
11. Shun-Lin Su, Charles H. Barry, Chi-Yuan Lo
    A space-efficient short-finding algorithm [VLSI layouts]. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:8, pp:1065-1068 [Journal]