Journals in DBLP

IEEE Trans. on CAD of Integrated Circuits and Systems
1990, volume: 9, number: 5

1. Christos A. Papachristou, Anil L. Pandya
   A design scheme for PLA-based control tables with reduced area and time-delay cost. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1990, v:9, n:5, pp:453-472 [Journal]
   
2. Philip A. Wilsey, Subrata Dasgupta
   A formal model of computer architectures for digital system design environments. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1990, v:9, n:5, pp:473-486 [Journal]
   
3. Kiyotaka Yamamura, Kazuo Horiuchi
   A globally and quadratically convergent algorithm for solving nonlinear resistive networks. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1990, v:9, n:5, pp:487-499 [Journal]
   
4. Khushro Shahookar, Pinaki Mazumder
   A genetic approach to standard cell placement using meta-genetic parameter optimization. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1990, v:9, n:5, pp:500-511 [Journal]
   
5. Wing Ning Li, Sartaj Sahni
   Pull up transistor folding. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1990, v:9, n:5, pp:512-521 [Journal]
   
6. Pei-Yung Hsiao, Wu-Shiung Feng
   Using a multiple storage quad tree on a hierarchical VLSI compaction scheme. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1990, v:9, n:5, pp:522-536 [Journal]
   
7. Paul Molitor
   Constrained via minimization for systolic arrays. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1990, v:9, n:5, pp:537-542 [Journal]
   
8. Ernst Rank, Ulrich Weinert
   A simulation system for diffusive oxidation of silicon: a two-dimensional finite element approach. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1990, v:9, n:5, pp:543-550 [Journal]
   
9. Anthony E. Parker, David J. Skellern
   An improved FET model for computer simulators. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1990, v:9, n:5, pp:551-553 [Journal]
   
10. Navneet K. Jain, V. C. Prasad, A. B. Bhattacharyya
    Delay time sensitivity in nonlinear monotone RC trees. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1990, v:9, n:5, pp:554-560 [Journal]