The SCEAS System
Navigation Menu

Journals in DBLP

IEEE Trans. on CAD of Integrated Circuits and Systems
2001, volume: 20, number: 10

  1. Wim F. J. Verhaegh, Emile H. L. Aarts, Paul C. N. van Gorp, Paul E. R. Lippens
    A two-stage solution approach to multidimensional periodicscheduling. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:10, pp:1185-1199 [Journal]
  2. Qinru Qiu, Q. Qu, Massoud Pedram
    Stochastic modeling of a power-managed system-construction andoptimization. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:10, pp:1200-1217 [Journal]
  3. Zilu Wu, Yumin Gao, Jinsheng Luo, Xun Hou, Guofu Chen
    Application of BEM to high-voltage junction termination. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:10, pp:1218-1225 [Journal]
  4. Pankaj Pant, Yuan-Chieh Hsu, Sandeep K. Gupta, Abhijit Chatterjee
    Path delay fault diagnosis in combinational circuits with implicitfault enumeration. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:10, pp:1226-1235 [Journal]
  5. Andrew B. Kahng, John Lach, William H. Mangione-Smith, Stefanus Mantik, Igor L. Markov, Miodrag Potkonjak, Paul Tucker, Huijuan Wang, Gregory Wolfe
    Constraint-based watermarking techniques for design IP protection. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:10, pp:1236-1252 [Journal]
  6. John Lach, William H. Mangione-Smith, Miodrag Potkonjak
    Fingerprinting techniques for field-programmable gate arrayintellectual property protection. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:10, pp:1253-1261 [Journal]
  7. Irith Pomeranz, Sudhakar M. Reddy
    Forward-looking fault simulation for improved static compaction. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:10, pp:1262-1265 [Journal]
  8. Guang-Ming Wu, Jai-Ming Lin, Yao-Wen Chang
    Generic ILP-based approaches for time-multiplexed FPGA partitioning. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:10, pp:1266-1274 [Journal]
NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002