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Journals in DBLP
- Wim F. J. Verhaegh, Emile H. L. Aarts, Paul C. N. van Gorp, Paul E. R. Lippens
A two-stage solution approach to multidimensional periodicscheduling. [Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:10, pp:1185-1199 [Journal]
- Qinru Qiu, Q. Qu, Massoud Pedram
Stochastic modeling of a power-managed system-construction andoptimization. [Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:10, pp:1200-1217 [Journal]
- Zilu Wu, Yumin Gao, Jinsheng Luo, Xun Hou, Guofu Chen
Application of BEM to high-voltage junction termination. [Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:10, pp:1218-1225 [Journal]
- Pankaj Pant, Yuan-Chieh Hsu, Sandeep K. Gupta, Abhijit Chatterjee
Path delay fault diagnosis in combinational circuits with implicitfault enumeration. [Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:10, pp:1226-1235 [Journal]
- Andrew B. Kahng, John Lach, William H. Mangione-Smith, Stefanus Mantik, Igor L. Markov, Miodrag Potkonjak, Paul Tucker, Huijuan Wang, Gregory Wolfe
Constraint-based watermarking techniques for design IP protection. [Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:10, pp:1236-1252 [Journal]
- John Lach, William H. Mangione-Smith, Miodrag Potkonjak
Fingerprinting techniques for field-programmable gate arrayintellectual property protection. [Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:10, pp:1253-1261 [Journal]
- Irith Pomeranz, Sudhakar M. Reddy
Forward-looking fault simulation for improved static compaction. [Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:10, pp:1262-1265 [Journal]
- Guang-Ming Wu, Jai-Ming Lin, Yao-Wen Chang
Generic ILP-based approaches for time-multiplexed FPGA partitioning. [Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:10, pp:1266-1274 [Journal]
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