Journals in DBLP

ACM Trans. Design Autom. Electr. Syst.
2003, volume: 8, number: 4

1. Shishpal Rawat, Hans-Joachim Wunderlich
   Introduction. [Citation Graph (0, 0)][DBLP]
   ACM Trans. Design Autom. Electr. Syst., 2003, v:8, n:4, pp:397-398 [Journal]
   
2. Sandeep Kumar Goel, Erik Jan Marinissen
   SOC test architecture design for efficient utilization of test bandwidth. [Citation Graph (0, 0)][DBLP]
   ACM Trans. Design Autom. Electr. Syst., 2003, v:8, n:4, pp:399-429 [Journal]
   
3. Aiman H. El-Maleh, Yahya E. Osais
   Test vector decomposition-based static compaction algorithms for combinational circuits. [Citation Graph (0, 0)][DBLP]
   ACM Trans. Design Autom. Electr. Syst., 2003, v:8, n:4, pp:430-459 [Journal]
   
4. Sudhakar M. Reddy, Kohei Miyase, Seiji Kajihara, Irith Pomeranz
   On test data volume reduction for multiple scan chain designs. [Citation Graph (0, 0)][DBLP]
   ACM Trans. Design Autom. Electr. Syst., 2003, v:8, n:4, pp:460-469 [Journal]
   
5. Lei Li, Krishnendu Chakrabarty, Nur A. Touba
   Test data compression using dictionaries with selective entries and fixed-length indices. [Citation Graph (0, 0)][DBLP]
   ACM Trans. Design Autom. Electr. Syst., 2003, v:8, n:4, pp:470-490 [Journal]
   
6. Adit D. Singh, Markus Seuring, Michael Gössel, Egor S. Sogomonyan
   Multimode scan: Test per clock BIST for IP cores. [Citation Graph (0, 0)][DBLP]
   ACM Trans. Design Autom. Electr. Syst., 2003, v:8, n:4, pp:491-505 [Journal]
   
7. Muhammad Nummer, Manoj Sachdev
   Testing high-performance pipelined circuits with slow-speed testers. [Citation Graph (0, 0)][DBLP]
   ACM Trans. Design Autom. Electr. Syst., 2003, v:8, n:4, pp:506-521 [Journal]
   
8. Kumar Parthasarathy, Turker Kuyel, Dana Price, Le Jin, Degang Chen, Randall L. Geiger
   BIST and production testing of ADCs using imprecise stimulus. [Citation Graph (0, 0)][DBLP]
   ACM Trans. Design Autom. Electr. Syst., 2003, v:8, n:4, pp:522-545 [Journal]
   
9. Zhuo Li, Xiang Lu, Wangqi Qiu, Weiping Shi, D. M. H. Walker
   A circuit level fault model for resistive bridges. [Citation Graph (0, 0)][DBLP]
   ACM Trans. Design Autom. Electr. Syst., 2003, v:8, n:4, pp:546-559 [Journal]
   
10. Dirk Niggemeyer, Elizabeth M. Rudnick
    A data acquisition methodology for on-chip repair of embedded memories. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2003, v:8, n:4, pp:560-576 [Journal]
    
11. Gustavo Neuberger, Fernanda Gusmão de Lima Kastensmidt, Luigi Carro, Ricardo Augusto da Luz Reis
    A multiple bit upset tolerant SRAM memory. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2003, v:8, n:4, pp:577-590 [Journal]