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Journals in DBLP

ACM Trans. Design Autom. Electr. Syst.
2005, volume: 10, number: 1

  1. Nikil D. Dutt
    Editorial. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2005, v:10, n:1, pp:1-2 [Journal]
  2. Jason Cong, Hui Huang, Xin Yuan
    Technology mapping and architecture evalution for k/m-macrocell-based FPGAs. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2005, v:10, n:1, pp:3-23 [Journal]
  3. Shanq-Jang Ruan, Kun-Lin Tsai, Edwin Naroska, Feipei Lai
    Bipartitioning and encoding in low-power pipelined circuits. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2005, v:10, n:1, pp:24-32 [Journal]
  4. Seda Ogrenci Memik, Ryan Kastner, Elaheh Bozorgzadeh, Majid Sarrafzadeh
    A scheduling algorithm for optimization and early planning in high-level synthesis. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2005, v:10, n:1, pp:33-57 [Journal]
  5. Saurabh N. Adya, Igor L. Markov
    Combinatorial techniques for mixed-size placement. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2005, v:10, n:1, pp:58-90 [Journal]
  6. Mehrdad Nourani, Mohammad H. Tehranipour
    RL-huffman encoding for test compression and power reduction in scan applications. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2005, v:10, n:1, pp:91-115 [Journal]
  7. Gene Eu Jan, Ki-Yin Chang, Su Gao, Ian Parberry
    A 4-geometry maze router and its application on multiterminal nets. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2005, v:10, n:1, pp:116-135 [Journal]
  8. Péter Arató, Zoltán Ádám Mann, András Orbán
    Algorithmic aspects of hardware/software partitioning. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2005, v:10, n:1, pp:136-156 [Journal]
  9. Dimitrios Kagaris
    A unified method for phase shifter computation. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2005, v:10, n:1, pp:157-167 [Journal]
  10. Chi-Chou Kao, Yen-Tai Lai
    An efficient algorithm for finding the minimal-area FPGA technology mapping. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2005, v:10, n:1, pp:168-186 [Journal]
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