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Journals in DBLP
- Majid Sarrafzadeh, Rajeev Jayaraman
Guest editorial. [Citation Graph (0, 0)][DBLP]
ACM Trans. Design Autom. Electr. Syst., 2002, v:7, n:4, pp:499-500 [Journal]
- Navin Vemuri, Priyank Kalla, Russell Tessier
BDD-based logic synthesis for LUT-based FPGAs. [Citation Graph (0, 0)][DBLP]
ACM Trans. Design Autom. Electr. Syst., 2002, v:7, n:4, pp:501-525 [Journal]
- Hongbing Fan, Jiping Liu, Yu-Liang Wu, C. K. Wong
Reduction design for generic universal switch blocks. [Citation Graph (0, 0)][DBLP]
ACM Trans. Design Autom. Electr. Syst., 2002, v:7, n:4, pp:526-546 [Journal]
- Andreas Dandalis, Viktor K. Prasanna
Run-time performance optimization of an FPGA-based deduction engine for SAT solvers. [Citation Graph (0, 0)][DBLP]
ACM Trans. Design Autom. Electr. Syst., 2002, v:7, n:4, pp:547-562 [Journal]
- Haibo Wang, Sarma B. K. Vrudhula
Behavioral synthesis of field programmable analog array circuits. [Citation Graph (0, 0)][DBLP]
ACM Trans. Design Autom. Electr. Syst., 2002, v:7, n:4, pp:563-604 [Journal]
- Ryan Kastner, Adam Kaplan, Seda Ogrenci Memik, Elaheh Bozorgzadeh
Instruction generation for hybrid reconfigurable systems. [Citation Graph (0, 0)][DBLP]
ACM Trans. Design Autom. Electr. Syst., 2002, v:7, n:4, pp:605-627 [Journal]
- Guang-Ming Wu, Jai-Ming Lin, Yao-Wen Chang
Performance-driven placement for dynamically reconfigurable FPGAs. [Citation Graph (0, 0)][DBLP]
ACM Trans. Design Autom. Electr. Syst., 2002, v:7, n:4, pp:628-642 [Journal]
- Amit Singh, Ganapathy Parthasarathy, Malgorzata Marek-Sadowska
Efficient circuit clustering for area and power reduction in FPGAs. [Citation Graph (0, 0)][DBLP]
ACM Trans. Design Autom. Electr. Syst., 2002, v:7, n:4, pp:643-663 [Journal]
- Shantanu Dutt, Vinay Verma, Hasan Arslan
A search-based bump-and-refit approach to incremental routing for ECO applications in FPGAs. [Citation Graph (0, 0)][DBLP]
ACM Trans. Design Autom. Electr. Syst., 2002, v:7, n:4, pp:664-693 [Journal]
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