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Journals in DBLP

ACM Trans. Design Autom. Electr. Syst.
2000, volume: 5, number: 1

  1. Luiz C. V. dos Santos, Marc J. M. Heijligers, C. A. J. van Eijk, J. Van Eijnhoven, Jochen A. G. Jess
    A code-motion pruning technique for global scheduling. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2000, v:5, n:1, pp:1-38 [Journal]
  2. Wen-Jong Fang, Allen C.-H. Wu
    Multiway FPGA partitioning by fully exploiting design hierarchy. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2000, v:5, n:1, pp:34-50 [Journal]
  3. Pao-Ann Hsiung
    CMAPS: a cosynthesis methodology for application-oriented parallel systems. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2000, v:5, n:1, pp:51-81 [Journal]
  4. Dinesh P. Mehta, Naveed A. Sherwani
    On the use of flexible, rectilinear blocks to obtain minimum-area floorplans in mixed block and cell designs. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2000, v:5, n:1, pp:82-97 [Journal]
  5. Sachin S. Sapatnekar, Weitong Chuang
    Power-delay optimizations in gate sizing. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2000, v:5, n:1, pp:98-114 [Journal]
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