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Journals in DBLP

ACM Trans. Design Autom. Electr. Syst.
1998, volume: 3, number: 2

  1. Pao-Ann Hsiung, Chung-Hwang Chen, Trong-Yen Lee, Sao-Jie Chen
    ICOS: an intelligent concurrent object-oriented synthesis methodology for multiprocessor systems. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 1998, v:3, n:2, pp:109-135 [Journal]
  2. Guido Araujo, Sharad Malik
    Code generation for fixed-point DSPs. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 1998, v:3, n:2, pp:136-161 [Journal]
  3. Giri Tiruvuri, Moon Chung
    Estimation of lower bounds in scheduling algorithms for high-level synthesis. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 1998, v:3, n:2, pp:162-180 [Journal]
  4. Frank Vahid, Thuy Dm Le, Yu-Chin Hsu
    Functional partitioning improvements over structural partitioning for packaging constraints and synthesis: tool performance. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 1998, v:3, n:2, pp:181-208 [Journal]
  5. Gernot Koch, Wolfgang Rosenstiel, Udo Kebschull
    Breakpoints and breakpoint detection in source-level emulation. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 1998, v:3, n:2, pp:209-230 [Journal]
  6. Irith Pomeranz, Sudhakar M. Reddy
    Functional test generation for delay faults in combinational circuits. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 1998, v:3, n:2, pp:231-248 [Journal]
  7. Xiao-Tao Chen, Fred J. Meyer, Fabrizio Lombardi
    Structural diagnosis of interconnects by coloring. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 1998, v:3, n:2, pp:249-271 [Journal]
  8. Dinesh P. Mehta
    Estimating the storage requirements of the rectangular and L-shaped corner stitching data structures. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 1998, v:3, n:2, pp:272-284 [Journal]
  9. Subhrajit Bhattacharya, Sujit Dey, Franc Brglez
    Effects of resource sharing on circuit delay: an assignment algorithm for clock period optimization. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 1998, v:3, n:2, pp:285-307 [Journal]
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