Journals in DBLP

ACM Trans. Design Autom. Electr. Syst.
2000, volume: 5, number: 3

1. Mary Jane Irwin
   Editorial. [Citation Graph (0, 0)][DBLP]
   ACM Trans. Design Autom. Electr. Syst., 2000, v:5, n:3, pp:265-266 [Journal]
   
2. R. Iris Bahar, Ernest T. Lampe, Enrico Macii
   Power optimization of technology-dependent circuits based on symbolic computation of logic implications. [Citation Graph (0, 0)][DBLP]
   ACM Trans. Design Autom. Electr. Syst., 2000, v:5, n:3, pp:267-293 [Journal]
   
3. M. Balakrishnan, Heman Khanna
   Allocation of FIFO structures in RTL data paths. [Citation Graph (0, 0)][DBLP]
   ACM Trans. Design Autom. Electr. Syst., 2000, v:5, n:3, pp:294-310 [Journal]
   
4. Luca Benini, Giovanni De Micheli
   Synthesis of low-power selectively-clocked systems from high-level specification. [Citation Graph (0, 0)][DBLP]
   ACM Trans. Design Autom. Electr. Syst., 2000, v:5, n:3, pp:311-321 [Journal]
   
5. Stephen A. Blythe, Robert A. Walker
   Efficient optimal design space characterization methodologies. [Citation Graph (0, 0)][DBLP]
   ACM Trans. Design Autom. Electr. Syst., 2000, v:5, n:3, pp:322-336 [Journal]
   
6. Alessandro Bogliolo, Luca Benini, Giovanni De Micheli
   Regression-based RTL power modeling. [Citation Graph (0, 0)][DBLP]
   ACM Trans. Design Autom. Electr. Syst., 2000, v:5, n:3, pp:337-372 [Journal]
   
7. Surendra Bommu, Niall O'Neill, Maciej J. Ciesielski
   Retiming-based factorization for sequential logic optimization. [Citation Graph (0, 0)][DBLP]
   ACM Trans. Design Autom. Electr. Syst., 2000, v:5, n:3, pp:373-398 [Journal]
   
8. Vincenza Carchiolo, Michele Malgeri, Giuseppe Mangioni
   Hardware/software synthesis of formal specifications in codesign of embedded systems. [Citation Graph (0, 0)][DBLP]
   ACM Trans. Design Autom. Electr. Syst., 2000, v:5, n:3, pp:399-432 [Journal]
   
9. Yao-Wen Chang, Kai Zhu, D. F. Wong
   Timing-driven routing for symmetrical array-based FPGAs. [Citation Graph (0, 0)][DBLP]
   ACM Trans. Design Autom. Electr. Syst., 2000, v:5, n:3, pp:433-450 [Journal]
   
10. Donald S. Gelosh, Dorothy E. Setliff
    Modeling layout tools to derive forward estimates of area and delay at the RTL level. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2000, v:5, n:3, pp:451-491 [Journal]
    
11. Guy Gogniat, Michel Auguin, Luc Bianco, Alain Pegatoquet
    A codesign back-end approach for embedded system design. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2000, v:5, n:3, pp:492-509 [Journal]
    
12. Avaneendra Gupta, John P. Hayes
    CLIP: integer-programming-based optimal layout synthesis of 2D CMOS cells. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2000, v:5, n:3, pp:510-547 [Journal]
    
13. Michael S. Hsiao, Elizabeth M. Rudnick, Janak H. Patel
    Dynamic state traversal for sequential circuit test generation. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2000, v:5, n:3, pp:548-565 [Journal]
    
14. Pradip K. Jha, Nikil D. Dutt
    High-level library mapping for memories. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2000, v:5, n:3, pp:566-603 [Journal]
    
15. Kumar N. Lalgudi, Marios C. Papaefthymiou, Miodrag Potkonjak
    Optimizing computations for effective block-processing. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2000, v:5, n:3, pp:604-630 [Journal]
    
16. David E. Long, Mahesh A. Iyer, Miron Abramovici
    FILL and FUNI: algorithms to identify illegal states and sequentially untestable faults. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2000, v:5, n:3, pp:631-657 [Journal]
    
17. Diana Marculescu, Radu Marculescu, Massoud Pedram
    Stochastic sequential machine synthesis with application to constrained sequence generation. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2000, v:5, n:3, pp:658-681 [Journal]
    
18. Preeti Ranjan Panda, Nikil D. Dutt, Alexandru Nicolau
    On-chip vs. off-chip memory: the data partitioning problem in embedded processor-based systems. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2000, v:5, n:3, pp:682-704 [Journal]
    
19. Richard Raimi, Ramin Hojati, Kedar S. Namjoshi
    Environment modeling and language universality. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2000, v:5, n:3, pp:705-725 [Journal]
    
20. Jin-Tai Yan
    Three-layer bubble-sorting-based nonManhattan channel routing. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2000, v:5, n:3, pp:726-734 [Journal]
    
21. Cheng-Hsing Yang, Sao-Jie Chen, Jan-Ming Ho, Chia-Chun Tsai
    Efficient routability check algorithms for segmented channel routing. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2000, v:5, n:3, pp:735-747 [Journal]