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Journals in DBLP

ACM Trans. Design Autom. Electr. Syst.
2005, volume: 10, number: 3

  1. JoAnn M. Paul, Donald E. Thomas, Andrew S. Cassidy
    High-level modeling and simulation of single-chip programmable heterogeneous multiprocessors. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2005, v:10, n:3, pp:431-461 [Journal]
  2. Arnab Roy, S. K. Panda, Rajeev Kumar, P. P. Chakrabarti
    A framework for systematic validation and debugging of pipeline simulators. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2005, v:10, n:3, pp:462-491 [Journal]
  3. Ansuman Banerjee, Pallab Dasgupta
    The open family of temporal logics: Annotating temporal operators with input constraints. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2005, v:10, n:3, pp:492-522 [Journal]
  4. Farinaz Koushanfar, Inki Hong, Miodrag Potkonjak
    Behavioral synthesis techniques for intellectual property protection. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2005, v:10, n:3, pp:523-545 [Journal]
  5. Puneet Gupta, Andrew B. Kahng, Stefanus Mantik
    Routing-aware scan chain ordering. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2005, v:10, n:3, pp:546-560 [Journal]
  6. Hua Xiang, Xiaoping Tang, Martin D. F. Wong
    An algorithm for integrated pin assignment and buffer planning. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2005, v:10, n:3, pp:561-572 [Journal]
  7. Jaehwan John Lee, Vincent John Mooney III
    An o(min(m, n)) parallel deadlock detection algorithm. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2005, v:10, n:3, pp:573-586 [Journal]
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