Journals in DBLP

ACM Trans. Design Autom. Electr. Syst.
2006, volume: 11, number: 1

1. Nikil D. Dutt
   Editorial. [Citation Graph (0, 0)][DBLP]
   ACM Trans. Design Autom. Electr. Syst., 2006, v:11, n:1, pp:1-2 [Journal]
   
2. Tony Givargis
   Zero cost indexing for improved processor cache performance. [Citation Graph (0, 0)][DBLP]
   ACM Trans. Design Autom. Electr. Syst., 2006, v:11, n:1, pp:3-25 [Journal]
   
3. George A. Constantinides
   Word-length optimization for differentiable nonlinear systems. [Citation Graph (0, 0)][DBLP]
   ACM Trans. Design Autom. Electr. Syst., 2006, v:11, n:1, pp:26-43 [Journal]
   
4. Qing Su, Jamil Kawa, Charles Chiang, Yehia Massoud
   Accurate modeling of substrate resistive coupling for floating substrates. [Citation Graph (0, 0)][DBLP]
   ACM Trans. Design Autom. Electr. Syst., 2006, v:11, n:1, pp:44-51 [Journal]
   
5. Azadeh Davoodi, Ankur Srivastava
   Effective techniques for the generalized low-power binding problem. [Citation Graph (0, 0)][DBLP]
   ACM Trans. Design Autom. Electr. Syst., 2006, v:11, n:1, pp:52-69 [Journal]
   
6. Patrick Schaumont, Doris Ching, Ingrid Verbauwhede
   An interactive codesign environment for domain-specific coprocessors. [Citation Graph (0, 0)][DBLP]
   ACM Trans. Design Autom. Electr. Syst., 2006, v:11, n:1, pp:70-87 [Journal]
   
7. Iris Hui-Ru Jiang, Song-Ra Pan, Yao-Wen Chang, Jing-Yang Jou
   Reliable crosstalk-driven interconnect optimization. [Citation Graph (0, 0)][DBLP]
   ACM Trans. Design Autom. Electr. Syst., 2006, v:11, n:1, pp:88-103 [Journal]
   
8. Dhananjay Kulkarni, Walid A. Najjar, Robert Rinker, Fadi J. Kurdahi
   Compile-time area estimation for LUT-based FPGAs. [Citation Graph (0, 0)][DBLP]
   ACM Trans. Design Autom. Electr. Syst., 2006, v:11, n:1, pp:104-122 [Journal]
   
9. Aviral Shrivastava, Partha Biswas, Ashok Halambi, Nikil D. Dutt, Alexandru Nicolau
   Compilation framework for code size reduction using reduced bit-width ISAs (rISAs). [Citation Graph (0, 0)][DBLP]
   ACM Trans. Design Autom. Electr. Syst., 2006, v:11, n:1, pp:123-146 [Journal]
   
10. Yi-Ping You, Chingren Lee, Jenq Kuen Lee
    Compilers for leakage power reduction. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2006, v:11, n:1, pp:147-164 [Journal]
    
11. Zili Shao, Bin Xiao, Chun Xue, Qingfeng Zhuge, Edwin Hsing-Mean Sha
    Loop scheduling with timing and switching-activity minimization for VLIW DSP. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2006, v:11, n:1, pp:165-185 [Journal]
    
12. Saraju P. Mohanty, N. Ranganathan, Sunil K. Chappidi
    ILP models for simultaneous energy and transient power minimization during behavioral synthesis. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2006, v:11, n:1, pp:186-212 [Journal]
    
13. Muhammet Mustafa Ozdal, Martin D. F. Wong
    Two-layer bus routing for high-speed printed circuit boards. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2006, v:11, n:1, pp:213-227 [Journal]
    
14. Mahmut T. Kandemir, J. Ramanujam, Ugur Sezer
    Improving the energy behavior of block buffering using compiler optimizations. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2006, v:11, n:1, pp:228-250 [Journal]