Journals in DBLP
Amit Chowdhary , John P. Hayes General technology mapping for field-programmable gate arrays based on lookup tables. [Citation Graph (0, 0)][DBLP ] Journal ] Maria K. Michael , Spyros Tragoudas ATPG tools for delay faults at the functional level. [Citation Graph (0, 0)][DBLP ] Journal ] Roman L. Lysecky , Frank Vahid Prefetching for improved bus wrapper performance in cores. [Citation Graph (0, 0)][DBLP ] Journal ] Shantanu Dutt , Wenyong Deng Cluster-aware iterative improvement techniques for partitioning large VLSI circuits. [Citation Graph (0, 0)][DBLP ] Journal ] Laurence Goodby , Alex Orailoglu , Paul M. Chau Microarchitectural synthesis of performance-constrained, low-power VLSI designs. [Citation Graph (0, 0)][DBLP ] Journal ] Luís Guerra e Silva , João P. Marques Silva , Luis Miguel Silveira , Karem A. Sakallah Satisfiability models and algorithms for circuit delay computation. [Citation Graph (0, 0)][DBLP ] Journal ] Alain Darte , Robert Schreiber , B. Ramakrishna Rau , Frédéric Vivien Constructing and exploiting linear schedules with prescribed parallelism. [Citation Graph (0, 0)][DBLP ] Journal ] Ashok Jagannathan , Sung-Woo Hur , John Lillis A fast algorithm for context-aware buffer insertion. [Citation Graph (0, 0)][DBLP ] Journal ] Ranga Vemuri , Srinivas Katkoori , Meenakshi Kaul , Jay Roy An efficient register optimization algorithm for high-level synthesis from hierarchical behavioral specifications. [Citation Graph (0, 0)][DBLP ] Journal ] Shi-Zheng Eric Lin , Chieh Changfan , Yu-Chin Hsu , Fur-Shing Tsai Optimal time borrowing analysis and timing budgeting optimization for latch-based designs. [Citation Graph (0, 0)][DBLP ] Journal ] 