Journals in DBLP
Jeff Alan Davis Guest Editorial. [Citation Graph (0, 0)][DBLP ] IEEE Trans. VLSI Syst., 2004, v:12, n:4, pp:337-338 [Journal ] Joni Dambre , Dirk Stroobandt , Jan Van Campenhout Toward the accurate prediction of placement wire length distributions in VLSI circuits. [Citation Graph (0, 0)][DBLP ] IEEE Trans. VLSI Syst., 2004, v:12, n:4, pp:339-348 [Journal ] Mario R. Casu , Mariagrazia Graziano , Guido Masera , Gianluca Piccinini , Maurizio Zamboni An electromigration and thermal model of power wires for a priori high-level reliability prediction. [Citation Graph (0, 0)][DBLP ] IEEE Trans. VLSI Syst., 2004, v:12, n:4, pp:349-358 [Journal ] Shamik Das , Anantha Chandrakasan , Rafael Reif Calibration of Rent's rule models for three-dimensional integrated circuits. [Citation Graph (0, 0)][DBLP ] IEEE Trans. VLSI Syst., 2004, v:12, n:4, pp:359-366 [Journal ] James W. Joyner , Payman Zarkesh-Ha , James D. Meindl Global interconnect design in a three-dimensional system-on-a-chip. [Citation Graph (0, 0)][DBLP ] IEEE Trans. VLSI Syst., 2004, v:12, n:4, pp:367-372 [Journal ] Suhrid A. Wadekar , Alice C. Parker Interconnect-based system-level energy and power prediction to guide architecture exploration. [Citation Graph (0, 0)][DBLP ] IEEE Trans. VLSI Syst., 2004, v:12, n:4, pp:373-380 [Journal ] PariVallal Kannan , Shankar Balachandran , Dinesh Bhatia On metrics for comparing interconnect estimation methods for FPGAs. [Citation Graph (0, 0)][DBLP ] IEEE Trans. VLSI Syst., 2004, v:12, n:4, pp:381-385 [Journal ] Andrey V. Mezhiba , Eby G. Friedman Scaling trends of on-chip power distribution noise. [Citation Graph (0, 0)][DBLP ] IEEE Trans. VLSI Syst., 2004, v:12, n:4, pp:386-394 [Journal ] Seongkyun Shin , Yungseon Eo , William R. Eisenstadt , Jongin Shim Analytical models and algorithms for the efficient signal integrity verification of inductance-effect-prominent multicoupled VLSI circuit interconnects. [Citation Graph (0, 0)][DBLP ] IEEE Trans. VLSI Syst., 2004, v:12, n:4, pp:395-407 [Journal ] Iouliia Skliarova , António de Brito Ferrari A software/reconfigurable hardware SAT solver. [Citation Graph (0, 0)][DBLP ] IEEE Trans. VLSI Syst., 2004, v:12, n:4, pp:408-419 [Journal ] Khaled Benkrid , Danny Crookes From application descriptions to hardware in seconds: a logic-based approach to bridging the gap. [Citation Graph (0, 0)][DBLP ] IEEE Trans. VLSI Syst., 2004, v:12, n:4, pp:420-436 [Journal ] Shizhong Mei , Yehea I. Ismail Modeling skin and proximity effects with reduced realizable RL circuits. [Citation Graph (0, 0)][DBLP ] IEEE Trans. VLSI Syst., 2004, v:12, n:4, pp:437-447 [Journal ]