Journals in DBLP

IEEE Trans. VLSI Syst.
2005, volume: 13, number: 6

1. Atanu Chattopadhyay, Zeljko Zilic
   GALDS: a complete framework for designing multiclock ASICs and SoCs. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2005, v:13, n:6, pp:641-654 [Journal]
   
2. Srinivasa R. Sridhara, Naresh R. Shanbhag
   Coding for system-on-chip networks: a unified framework. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2005, v:13, n:6, pp:655-667 [Journal]
   
3. Yangdong Deng, W. P. Maly
   2.5-dimensional VLSI system integration. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2005, v:13, n:6, pp:668-677 [Journal]
   
4. Qiang Xu, Nicola Nicolici
   Wrapper design for multifrequency IP cores. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2005, v:13, n:6, pp:678-685 [Journal]
   
5. Chip-Hong Chang, Jiangmin Gu, Mingyan Zhang
   A review of 0.18-/spl mu/m full adder performances for tree structured arithmetic circuits. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2005, v:13, n:6, pp:686-695 [Journal]
   
6. Haris Lekatsas, Jörg Henkel, Wayne Wolf
   Approximate arithmetic coding for bus transition reduction in low power designs. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2005, v:13, n:6, pp:696-707 [Journal]
   
7. J. Chien-Mo Li
   Diagnosis of single stuck-at faults and multiple timing faults in scan chains. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2005, v:13, n:6, pp:708-718 [Journal]
   
8. Mohammad Tehranipoor, Mehrdad Nourani, Krishnendu Chakrabarty
   Nine-coded compression technique for testing embedded cores in SoCs. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2005, v:13, n:6, pp:719-731 [Journal]
   
9. Shyue-Kung Lu, Jen-Sheng Shih, Shih-Chang Huang
   Design-for-testability and fault-tolerant techniques for FFT processors. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2005, v:13, n:6, pp:732-741 [Journal]
   
10. Jin-Fu Li, Jen-Chieh Yeh, Rei-Fu Huang, Cheng-Wen Wu
    A built-in self-repair design for RAMs with 2-D redundancy. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2005, v:13, n:6, pp:742-745 [Journal]
    
11. Anh Dinh, Xiao Hu
    A hardware-efficient technique to implement a trellis code modulation decoder. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2005, v:13, n:6, pp:745-750 [Journal]
    
12. Rishi Chaturvedi, Jiang Hu
    An efficient merging scheme for prescribed skew clock routing. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2005, v:13, n:6, pp:750-754 [Journal]
    
13. Vojin G. Oklobdzija, Bart R. Zeydel, Hoang Q. Dao, Sanu Mathew, Ram Krishnamurthy
    Comparison of high-performance VLSI adders in the energy-delay space. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2005, v:13, n:6, pp:754-758 [Journal]
    
14. S. W. Oldridge, S. J. E. Wilton
    A novel FPGA architecture supporting wide, shallow memories. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2005, v:13, n:6, pp:758-762 [Journal]
    
15. Vishal Khandelwal, Azadeh Davoodi, Ankur Srivastava
    Simultaneous V/sub t/ selection and assignment for leakage optimization. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2005, v:13, n:6, pp:762-765 [Journal]
    
16. Dmitri Maslov, Gerhard W. Dueck, D. Michael Miller
    Synthesis of Fredkin-Toffoli reversible networks. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2005, v:13, n:6, pp:765-769 [Journal]